flashrom

flashrom@flashrom.org

5 participants
9161 discussions

Getting Started With Coreboot
by Schenk, John 24 Mar '11

24 Mar '11

To whom it may concern: If the motherboard or main board is not seen in the list of tested or supported boards does this suggest that Flashrom may not work? If no, is it possible I could exchange emails with you for help in attempting to Flash Coreboot on this main board Bios chip? If not Coreboot, I would still like to learn how to use Flashrom, if I could. I am running Ubuntu 9.04 on a on an older 2007 gateway laptop together with an Xp Windows platform. After viewing your helpful video I agree that removing the existing non trustable Bios makes clear sense, and the sooner the better. Yes, I do program in C. Final comment, Coreboot should be in all microprocessor based devices from the get go. God Bless! John

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[PATCH] DirectIO is now called DirectHW
by Carl-Daniel Hailfinger 21 Mar '11

21 Mar '11

Stefan made me aware of this patch. I'm reposting it to the list. Stefan, can you commit? I already added my ack below. Update port of flashrom package to Mac OS X using DirectHW: http://www.coreboot.org/DirectHW Signed-off-by: Stefan Reinauer<stefan.reinauer(a)coreboot.org> Acked-by: Carl-Daniel Hailfinger<c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-r1280/hwaccess.h =================================================================== --- flashrom-r1280/hwaccess.h +++ flashrom-r1280/hwaccess.h @@ -194,7 +194,7 @@ #else #if defined(__DARWIN__) /* Header is part of the DirectHW library. */ - #include<DirectIO/darwinio.h> + #include<DirectHW/DirectHW.h> #define off64_t off_t #define lseek64 lseek #endif Index: flashrom-r1280/Makefile =================================================================== --- flashrom-r1280/Makefile +++ flashrom-r1280/Makefile @@ -44,8 +44,8 @@ endif ifeq ($(OS_ARCH), Darwin) CPPFLAGS += -I/opt/local/include -I/usr/local/include -# DirectIO framework can be found in the DirectHW library. -LDFLAGS += -framework IOKit -framework DirectIO -L/opt/local/lib -L/usr/local/lib +# DirectHW framework can be found in the DirectHW library. +LDFLAGS += -framework IOKit -framework DirectHW -L/opt/local/lib -L/usr/local/lib endif ifeq ($(OS_ARCH), FreeBSD) CPPFLAGS += -I/usr/local/include Index: flashrom-r1280/physmap.c =================================================================== --- flashrom-r1280/physmap.c +++ flashrom-r1280/physmap.c @@ -134,7 +134,7 @@ } #elif defined(__DARWIN__) -#define MEM_DEV "DirectIO" +#define MEM_DEV "DirectHW" static void *sys_physmap(unsigned long phys_addr, size_t len) { -- http://www.hailfinger.org/

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flashrom & eee pc 900
by Алексей Харьковский 20 Mar '11

20 Mar '11

Hello. I can't see support eee pc 900 in hardware support list. Eee PC 701 4G is BAD. My log: localhost ~ # flashrom -r old_bios.binflashrom v0.9.3-r1205 on Linux 2.6.30-gentoo-r4 (i686), built with libpci 3.1.4, GCC 4.4.1, little endianflashrom is free software, get the source code at http://www.flashrom.org (http://www.flashrom.org) Calibrating delay loop... delay loop is unreliable, trying to continue OK.No coreboot table found.Found chipset "Intel ICH6-M", enabling flash write... OK.This chipset supports the following protocols: FWH.No EEPROM/flash device found.Note: flashrom can never write if the flash chip isn't found automatically. Is ASUS Eee PC 900 not support, or i have wrong kernel config? -- Читайте и отправляйте электронные письма прямо со своего телефона. Просто зайдите с телефона на m.mail.ru

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[commit] r1282 - trunk
by repository service 19 Mar '11

19 Mar '11

Author: stepan Date: Fri Mar 18 23:00:15 2011 New Revision: 1282 URL: http://flashrom.org/trac/flashrom/changeset/1282 Log: Update port of flashrom package to Mac OS X using DirectHW: http://www.coreboot.org/DirectHW Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Modified: trunk/Makefile trunk/hwaccess.h trunk/physmap.c Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Thu Mar 17 01:10:25 2011 (r1281) +++ trunk/Makefile Fri Mar 18 23:00:15 2011 (r1282) @@ -44,8 +44,8 @@ endif ifeq ($(OS_ARCH), Darwin) CPPFLAGS += -I/opt/local/include -I/usr/local/include -# DirectIO framework can be found in the DirectHW library. -LDFLAGS += -framework IOKit -framework DirectIO -L/opt/local/lib -L/usr/local/lib +# DirectHW framework can be found in the DirectHW library. +LDFLAGS += -framework IOKit -framework DirectHW -L/opt/local/lib -L/usr/local/lib endif ifeq ($(OS_ARCH), FreeBSD) CPPFLAGS += -I/usr/local/include Modified: trunk/hwaccess.h ============================================================================== --- trunk/hwaccess.h Thu Mar 17 01:10:25 2011 (r1281) +++ trunk/hwaccess.h Fri Mar 18 23:00:15 2011 (r1282) @@ -194,7 +194,7 @@ #else #if defined(__DARWIN__) /* Header is part of the DirectHW library. */ - #include <DirectIO/darwinio.h> + #include <DirectHW/DirectHW.h> #define off64_t off_t #define lseek64 lseek #endif Modified: trunk/physmap.c ============================================================================== --- trunk/physmap.c Thu Mar 17 01:10:25 2011 (r1281) +++ trunk/physmap.c Fri Mar 18 23:00:15 2011 (r1282) @@ -134,7 +134,7 @@ } #elif defined(__DARWIN__) -#define MEM_DEV "DirectIO" +#define MEM_DEV "DirectHW" static void *sys_physmap(unsigned long phys_addr, size_t len) {

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coreboot GSoC 2011
by Marc Jones 18 Mar '11

18 Mar '11

I'm happy to announce that coreboot has been accepted to participate in GSoC 2011. Please forward this information to all prospective GSoC student participants. Note, the coreboot project acts as an umbrella for coreboot related projects like flashrom and other payloads. http://www.google-melange.com/gsoc/org/show/google/gsoc2011/coreboot Prospective students and mentors should visit the coreboot wiki for complete information. http://www.coreboot.org/GSoC Please feel free to update the wiki or email the coreboot list if you have additional project ideas or other comments. Regards, Marc -- http://se-eng.com

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thinkpad T410s + intel dg54id
by Stefan Tauner 17 Mar '11

17 Mar '11

i have attached flashrom's output below. patch is in the following mail. ======== DG45ID ======== ./flashrom -c "W25x32" -r ../testimages/dg45id.orig.img -VV Checking for a C compiler... found. Checking for libpci headers... found. Checking if libpci is present and sufficient... yes. Checking for FTDI support... not found. Checking for utsname support... found. flashrom v0.9.3-runknown on Linux 2.6.34-020634-generic (x86_64), built with libpci 3.0.0, GCC 4.4.3, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 2662M loops per second, 10 myus = 11 us, 100 myus = 101 us, 1000 myus = 999 us, 10000 myus = 10028 us, 4 myus = 4 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: " " DMI string system-product-name: " " DMI string system-version: " " DMI string baseboard-manufacturer: "Intel Corporation" DMI string baseboard-product-name: "DG45ID" DMI string baseboard-version: "AAE27729-307" DMI string chassis-type: "Desktop" Found chipset "Intel ICH10R", enabling flash write... chipset PCI ID is 8086:3a16, 0xfff80000/0xffb80000 FWH IDSEL: 0x0 0xfff00000/0xffb00000 FWH IDSEL: 0x0 0xffe80000/0xffa80000 FWH IDSEL: 0x1 0xffe00000/0xffa00000 FWH IDSEL: 0x1 0xffd80000/0xff980000 FWH IDSEL: 0x2 0xffd00000/0xff900000 FWH IDSEL: 0x2 0xffc80000/0xff880000 FWH IDSEL: 0x3 0xffc00000/0xff800000 FWH IDSEL: 0x3 0xff700000/0xff300000 FWH IDSEL: 0x4 0xff600000/0xff200000 FWH IDSEL: 0x5 0xff500000/0xff100000 FWH IDSEL: 0x6 0xff400000/0xff000000 FWH IDSEL: 0x7 0xfff80000/0xffb80000 FWH decode enabled 0xfff00000/0xffb00000 FWH decode enabled 0xffe80000/0xffa80000 FWH decode enabled 0xffe00000/0xffa00000 FWH decode disabled 0xffd80000/0xff980000 FWH decode disabled 0xffd00000/0xff900000 FWH decode disabled 0xffc80000/0xff880000 FWH decode disabled 0xffc00000/0xff800000 FWH decode disabled 0xff700000/0xff300000 FWH decode disabled 0xff600000/0xff200000 FWH decode disabled 0xff500000/0xff100000 FWH decode disabled 0xff400000/0xff000000 FWH decode disabled Maximum FWH chip size: 0x100000 bytes BIOS Lock Enable: enabled, BIOS Write Enable: disabled, BIOS_CNTL is 0x2 Root Complex Register Block address = 0xfed1c000 GCS = 0xc1465: BIOS Interface Lock-Down: enabled, BOOT BIOS Straps: 0x1 (SPI) Top Swap : not enabled SPIBAR = 0xfed1c000 + 0x3800 0x04: 0xe008 (HSFS) FLOCKDN 1, FDV 1, FDOPSS 1, SCIP 0, BERASE 1, AEL 0, FCERR 0, FDONE 0 0x50: 0x00001a1b (FRAP) BMWAG 0x00, BMRAG 0x00, BRWA 0x1a, BRRA 0x1b 0x54: 0x00000000 (FREG0: Flash Descriptor) 0x00000000-0x00000fff is read-only 0x58: 0x03ff0280 (FREG1: BIOS) 0x00280000-0x003fffff is read-write 0x5C: 0x027f0003 (FREG2: Management Engine) 0x00003000-0x0027ffff is locked 0x60: 0x00020001 (FREG3: Gigabit Ethernet) 0x00001000-0x00002fff is read-write 0x64: 0x00000fff (FREG4: Platform Data) 0x00fff000-0x00000fff is read-write 0x74: 0x00000000 (PR0) 0x78: 0x00000000 (PR1) 0x7C: 0x00000000 (PR2) 0x80: 0x00000000 (PR3) 0x84: 0x00000000 (PR4) 0x90: 0x00401000 (SSFS, SSFC) 0x94: 0x0006 (PREOP) 0x96: 0x043b (OPTYPE) 0x98: 0x05200302 (OPMENU) 0x9C: 0x0000019f (OPMENU+4) 0xA0: 0x00000000 (BBAR) 0xB0: 0x00004000 (FDOC) WARNING: SPI Configuration Lockdown activated. Reading OPCODES... done preop0=0x06, preop1=0x00 op[0]=0x02, 3, 0 op[1]=0x03, 2, 0 op[2]=0x20, 3, 0 op[3]=0x05, 0, 0 op[4]=0x9f, 0, 0 op[5]=0x01, 1, 0 op[6]=0x00, 0, 0 op[7]=0x00, 0, 0 SPI Read Configuration: prefetching disabled, caching enabled, OK. This chipset supports the following protocols: FWH,SPI. Probing for Winbond W25x32, 4096 kB: RDID returned 0xef 0x30 0x16. probe_spi_rdid_generic: id1 0xef, id2 0x3016 Chip status register is 00 Found chip "Winbond W25x32" (4096 kB, SPI) at physical address 0xffc00000. === This flash part has status UNTESTED for operations: READ ERASE WRITE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -Vr, -Vw, -VE), and mention which mainboard or programmer you tested. Please mention your board in the subject line. Thanks for your help! Reading flash... Transaction error SSFS SCIP=1, CDS=1, FCERR=1, AEL=1 | SSFC SCGO=1, ACS=1, SPOP=1, COP=7, DBC=63, SME=1, SCF=7 run OPCODE 0x03 failed at address 0x003000. Read operation failed! FAILED. Restoring PCI config space for 00:1f:0 reg 0xdc =============== t410s ========== ./flashrom -Vfp internal:laptop=force_I_want_a_brick -r ../testimages/t410s.img -V -c "W25x64" flashrom v0.9.3-r1280 on Linux 2.6.35-27-generic (x86_64), built with libpci 3.1.7, GCC 4.4.5, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 1195M loops per second, 10 myus = 10 us, 100 myus = 100 us, 1000 myus = 999 us, 10000 myus = 10009 us, 4 myus = 4 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "LENOVO" DMI string system-product-name: "2924W33" DMI string system-version: "ThinkPad T410s" DMI string baseboard-manufacturer: "LENOVO" DMI string baseboard-product-name: "2924W33" DMI string baseboard-version: "Not Available" DMI string chassis-type: "Notebook" Laptop detected via DMI ======================================================================== WARNING! You seem to be running flashrom on a laptop. Laptops, notebooks and netbooks are difficult to support and we recommend to use the vendor flashing utility. The embedded controller (EC) in these machines often interacts badly with flashing. See http://www.flashrom.org/Laptops for details. If flash is shared with the EC, erase is guaranteed to brick your laptop and write may brick your laptop. Read and probe may irritate your EC and cause fan failure, backlight failure and sudden poweroff. You have been warned. ======================================================================== Proceeding anyway because user specified laptop=force_I_want_a_brick Found chipset "Intel QS57", enabling flash write... chipset PCI ID is 8086:3b0f, 0xfff80000/0xffb80000 FWH IDSEL: 0x0 0xfff00000/0xffb00000 FWH IDSEL: 0x0 0xffe80000/0xffa80000 FWH IDSEL: 0x0 0xffe00000/0xffa00000 FWH IDSEL: 0x0 0xffd80000/0xff980000 FWH IDSEL: 0x0 0xffd00000/0xff900000 FWH IDSEL: 0x0 0xffc80000/0xff880000 FWH IDSEL: 0x0 0xffc00000/0xff800000 FWH IDSEL: 0x0 0xff700000/0xff300000 FWH IDSEL: 0x4 0xff600000/0xff200000 FWH IDSEL: 0x5 0xff500000/0xff100000 FWH IDSEL: 0x6 0xff400000/0xff000000 FWH IDSEL: 0x7 0xfff80000/0xffb80000 FWH decode enabled 0xfff00000/0xffb00000 FWH decode enabled 0xffe80000/0xffa80000 FWH decode enabled 0xffe00000/0xffa00000 FWH decode enabled 0xffd80000/0xff980000 FWH decode enabled 0xffd00000/0xff900000 FWH decode enabled 0xffc80000/0xff880000 FWH decode enabled 0xffc00000/0xff800000 FWH decode enabled 0xff700000/0xff300000 FWH decode enabled 0xff600000/0xff200000 FWH decode enabled 0xff500000/0xff100000 FWH decode enabled 0xff400000/0xff000000 FWH decode enabled Maximum FWH chip size: 0x400000 bytes BIOS Lock Enable: disabled, BIOS Write Enable: disabled, BIOS_CNTL is 0x0 Root Complex Register Block address = 0xfed1c000 GCS = 0xc61: BIOS Interface Lock-Down: enabled, BOOT BIOS Straps: 0x3 (LPC) Top Swap : not enabled SPIBAR = 0xfed1c000 + 0x3800 0x04: 0xe008 (HSFS) FLOCKDN 1, FDV 1, FDOPSS 1, SCIP 0, BERASE 1, AEL 0, FCERR 0, FDONE 0 0x50: 0x00000a0b (FRAP) BMWAG 0x00, BMRAG 0x00, BRWA 0x0a, BRRA 0x0b 0x54: 0x00000000 (FREG0: Flash Descriptor) 0x00000000-0x00000fff is read-only 0x58: 0x07ff0500 (FREG1: BIOS) 0x00500000-0x007fffff is read-write 0x5C: 0x04ff0003 (FREG2: Management Engine) 0x00003000-0x004fffff is locked 0x60: 0x00020001 (FREG3: Gigabit Ethernet) 0x00001000-0x00002fff is read-write 0x64: 0x00000fff (FREG4: Platform Data) 0x00fff000-0x00000fff is locked 0x74: 0x9fff07d0 (PR0) 0x78: 0x00000000 (PR1) 0x7C: 0x00000000 (PR2) 0x80: 0x00000000 (PR3) 0x84: 0x00000000 (PR4) 0x90: 0xf87f100c (SSFS, SSFC) 0x94: 0x5006 (PREOP) 0x96: 0x143b (OPTYPE) 0x98: 0x05200302 (OPMENU) 0x9C: 0x0601209f (OPMENU+4) 0xA0: 0x00000000 (BBAR) 0xB0: 0x00000004 (FDOC) WARNING: SPI Configuration Lockdown activated. Reading OPCODES... done preop0=0x06, preop1=0x50 op[0]=0x02, 3, 0 op[1]=0x03, 2, 0 op[2]=0x20, 3, 0 op[3]=0x05, 0, 0 op[4]=0x9f, 0, 0 op[5]=0x20, 1, 0 op[6]=0x01, 1, 0 op[7]=0x06, 0, 0 SPI Read Configuration: prefetching disabled, caching enabled, OK. This chipset supports the following protocols: FWH,SPI. Probing for Winbond W25x64, 8192 kB: RDID returned 0xef 0x30 0x17. probe_spi_rdid_generic: id1 0xef, id2 0x3017 Chip status register is 00 Found chip "Winbond W25x64" (8192 kB, SPI) at physical address 0xff800000. === This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -Vr, -Vw, -VE), and mention which mainboard or programmer you tested. Please mention your board in the subject line. Thanks for your help! Reading flash... Transaction error! SSFS: SCIP=1, FDONE=1, FCERR=1, AEL=1 | SSFC: SCGO=1, ACS=1, SPOP=1, COP=7, DBC=63, SME=1, SCF=7 run OPCODE 0x03 failed at address 0x003000. Read operation failed! FAILED. Restoring PCI config space for 00:1f:0 reg 0xdc Stefan Tauner (1): add status of Thinkpad T410s and DG45ID to the wiki table print.c | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-)

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[commit] r1281 - trunk
by repository service 17 Mar '11

17 Mar '11

Author: hailfinger Date: Thu Mar 17 01:10:25 2011 New Revision: 1281 URL: http://flashrom.org/trac/flashrom/changeset/1281 Log: Proper error handling for ICH/VIA SPI: Use 16-bit values for bit masks in 16-bit registers. Check for SPI Cycle In Progress and wait up to 60 ms. Do not touch reserved bits. Reduce SPI cycle timeout from 60 s to 60 ms. Clear transaction errors caused by our own SPI accesses. Add better debugging in case the hardware misbehaves. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Acked-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Modified: trunk/ichspi.c Modified: trunk/ichspi.c ============================================================================== --- trunk/ichspi.c Tue Mar 8 08:17:44 2011 (r1280) +++ trunk/ichspi.c Thu Mar 17 01:10:25 2011 (r1281) @@ -51,6 +51,7 @@ #define SSFS_CDS 0x00000004 #define SSFS_FCERR 0x00000008 #define SSFS_AEL 0x00000010 +#define SSFS_RESERVED_MASK 0x000000e2 #define ICH9_REG_SSFC 0x91 /* 24 Bits */ #define SSFC_SCGO 0x00000200 @@ -63,6 +64,7 @@ #define SSFC_SCF 0x01000000 #define SSFC_SCF_20MHZ 0x00000000 #define SSFC_SCF_33MHZ 0x01000000 +#define SSFC_RESERVED_MASK 0xf8008100 #define ICH9_REG_PREOP 0x94 /* 16 Bits */ #define ICH9_REG_OPTYPE 0x96 /* 16 Bits */ @@ -76,9 +78,11 @@ // ICH7 registers #define ICH7_REG_SPIS 0x00 /* 16 Bits */ -#define SPIS_SCIP 0x00000001 -#define SPIS_CDS 0x00000004 -#define SPIS_FCERR 0x00000008 +#define SPIS_SCIP 0x0001 +#define SPIS_GRANT 0x0002 +#define SPIS_CDS 0x0004 +#define SPIS_FCERR 0x0008 +#define SPIS_RESERVED_MASK 0x7ff0 /* VIA SPI is compatible with ICH7, but maxdata to transfer is 16 bytes. @@ -146,6 +150,11 @@ return mmio_readw(ich_spibar + X); } +static uint16_t REGREAD8(int X) +{ + return mmio_readb(ich_spibar + X); +} + #define REGWRITE32(X,Y) mmio_writel(Y, ich_spibar+X) #define REGWRITE16(X,Y) mmio_writew(Y, ich_spibar+X) #define REGWRITE8(X,Y) mmio_writeb(Y, ich_spibar+X) @@ -497,6 +506,15 @@ write_cmd = 1; } + timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */ + while ((REGREAD16(ICH7_REG_SPIS) & SPIS_SCIP) && --timeout) { + programmer_delay(10); + } + if (!timeout) { + msg_perr("Error: SCIP never cleared!\n"); + return 1; + } + /* Programm Offset in Flash into FADDR */ REGWRITE32(ICH7_REG_SPIA, (offset & 0x00FFFFFF)); /* SPI addresses are 24 BIT only */ @@ -523,7 +541,9 @@ } /* Assemble SPIS */ - temp16 = 0; + temp16 = REGREAD16(ICH7_REG_SPIS); + /* keep reserved bits */ + temp16 &= SPIS_RESERVED_MASK; /* clear error status registers */ temp16 |= (SPIS_CDS + SPIS_FCERR); REGWRITE16(ICH7_REG_SPIS, temp16); @@ -570,18 +590,26 @@ /* write it */ REGWRITE16(ICH7_REG_SPIC, temp16); - /* wait for cycle complete */ - timeout = 100 * 1000 * 60; // 60s is a looong timeout. - while (((REGREAD16(ICH7_REG_SPIS) & SPIS_CDS) == 0) && --timeout) { + /* Wait for Cycle Done Status or Flash Cycle Error. */ + timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */ + while (((REGREAD16(ICH7_REG_SPIS) & (SPIS_CDS | SPIS_FCERR)) == 0) && + --timeout) { programmer_delay(10); } if (!timeout) { - msg_perr("timeout\n"); + msg_perr("timeout, ICH7_REG_SPIS=0x%04x\n", + REGREAD16(ICH7_REG_SPIS)); + return 1; } /* FIXME: make sure we do not needlessly cause transaction errors. */ - if ((REGREAD16(ICH7_REG_SPIS) & SPIS_FCERR) != 0) { - msg_pdbg("Transaction error!\n"); + temp16 = REGREAD16(ICH7_REG_SPIS); + if (temp16 & SPIS_FCERR) { + msg_perr("Transaction error for opcode 0x%02x!\n", + op.opcode); + /* keep reserved bits */ + temp16 &= SPIS_RESERVED_MASK; + REGWRITE16(ICH7_REG_SPIS, temp16 | SPIS_FCERR); return 1; } @@ -616,6 +644,15 @@ write_cmd = 1; } + timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */ + while ((REGREAD8(ICH9_REG_SSFS) & SSFS_SCIP) && --timeout) { + programmer_delay(10); + } + if (!timeout) { + msg_perr("Error: SCIP never cleared!\n"); + return 1; + } + /* Programm Offset in Flash into FADDR */ REGWRITE32(ICH9_REG_FADDR, (offset & 0x00FFFFFF)); /* SPI addresses are 24 BIT only */ @@ -641,12 +678,13 @@ } /* Assemble SSFS + SSFC */ - /* keep reserved bits (23-19,7,0) */ temp32 = REGREAD32(ICH9_REG_SSFS); - temp32 &= 0xF8008100; - + /* keep reserved bits */ + temp32 &= SSFS_RESERVED_MASK | SSFC_RESERVED_MASK; /* clear error status registers */ temp32 |= (SSFS_CDS + SSFS_FCERR); + REGWRITE32(ICH9_REG_SSFS, temp32); + /* Use 20 MHz */ temp32 |= SSFC_SCF_20MHZ; @@ -691,18 +729,27 @@ /* write it */ REGWRITE32(ICH9_REG_SSFS, temp32); - /*wait for cycle complete */ - timeout = 100 * 1000 * 60; // 60s is a looong timeout. - while (((REGREAD32(ICH9_REG_SSFS) & SSFS_CDS) == 0) && --timeout) { + /* Wait for Cycle Done Status or Flash Cycle Error. */ + timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */ + while (((REGREAD32(ICH9_REG_SSFS) & (SSFS_CDS | SSFS_FCERR)) == 0) && + --timeout) { programmer_delay(10); } if (!timeout) { - msg_perr("timeout\n"); + msg_perr("timeout, ICH9_REG_SSFS=0x%08x\n", + REGREAD32(ICH9_REG_SSFS)); + return 1; } /* FIXME make sure we do not needlessly cause transaction errors. */ - if ((REGREAD32(ICH9_REG_SSFS) & SSFS_FCERR) != 0) { - msg_pdbg("Transaction error!\n"); + temp32 = REGREAD32(ICH9_REG_SSFS); + if (temp32 & SSFS_FCERR) { + msg_perr("Transaction error for opcode 0x%02x!\n", + op.opcode); + /* keep reserved bits */ + temp32 &= SSFS_RESERVED_MASK | SSFC_RESERVED_MASK; + /* Clear the transaction error. */ + REGWRITE32(ICH9_REG_SSFS, temp32 | SSFS_FCERR); return 1; } @@ -1042,7 +1089,6 @@ msg_pdbg("0x%02x: 0x%08x (PBR%d)\n", offs, mmio_readl(ich_spibar + offs), i); } - msg_pdbg("\n"); if (mmio_readw(ich_spibar) & (1 << 15)) { msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n"); ichspi_lock = 1; @@ -1082,8 +1128,20 @@ mmio_readl(ich_spibar + 0x80)); msg_pdbg("0x84: 0x%08x (PR4)\n", mmio_readl(ich_spibar + 0x84)); - msg_pdbg("0x90: 0x%08x (SSFS, SSFC)\n", - mmio_readl(ich_spibar + 0x90)); + + tmp = mmio_readl(ich_spibar + 0x90); + msg_pdbg("0x90: 0x%02x (SSFS)\n", tmp & 0xff); + msg_pdbg("AEL %i, ", (tmp >> 4) & 1); + msg_pdbg("FCERR %i, ", (tmp >> 3) & 1); + msg_pdbg("FDONE %i, ", (tmp >> 2) & 1); + msg_pdbg("SCIP %i\n", (tmp >> 0) & 1); + if (tmp & (1 << 3)) { + msg_pdbg("Clearing SSFS.FCERR\n"); + mmio_writeb(1 << 3, ich_spibar + 0x90); + } + tmp >>= 8; + msg_pdbg("0x91: 0x%06x (SSFC)\n", tmp); + msg_pdbg("0x94: 0x%04x (PREOP)\n", mmio_readw(ich_spibar + 0x94)); msg_pdbg("0x96: 0x%04x (OPTYPE)\n",

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flashrom compiled without dependencies
by Wop Byte 16 Mar '11

16 Mar '11

Is there a way to compile flashrom so that it statically includes the needed libraries? I need to run this on multiple (over 200) machines that runs a slim version of linux and they dont have internet access so I can just install it. If this isnt possible can it be packaged to run as a self extracting file? thanks wopr

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[PATCH 0/8] retry
by Stefan Tauner 15 Mar '11

15 Mar '11

ooops again. i missed that git send-email did not get the RCPT TO header correctly and did only send it to me last night. so here it is really. finally. please. :) Stefan Tauner (8): whitespace, documentation and other small stuff The AT25F512B is quite different from the other (yet unsupported) chips in the AT25F* familiy, so rename 512B-specific stuff. generify spi_rdid to allow passing different opcodes. This is needed to add support for Atmel's AT25F series. Add support for Atmel's AT25F series of SPI flash chips. This includes a new probing method (probe_spi_rdid_at25f), block erase method (spi_block_erase_62), spi_prettyprint_status_register_at25f and spi_disable_blockprotect_at25f. add support for 8086:1076 (82541GI) to nicintel_spi.c use getpagesize() to determine physmap's length in nicintel_spi.c check if write enable is really set in nicintel_spi_init (and minor comment changes). Added (N) to the name of MX29F002B/T devices. chipdrivers.h | 3 + chipset_enable.c | 4 +- drkaiser.c | 2 +- flash.h | 7 ++- flashchips.c | 93 ++++++++++++++++++++++++++++- flashchips.h | 18 +++--- flashrom.c | 4 +- nicintel_spi.c | 23 ++++++- print.c | 2 +- print_wiki.c | 2 +- spi.h | 14 +++- spi25.c | 177 ++++++++++++++++++++++++++++++++++++++++++++++------- wbsio_spi.c | 2 +- 13 files changed, 298 insertions(+), 53 deletions(-)

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[PATCH 0/7] Hello, Support for Atmel's AT25F series and some small stuff
by Stefan Tauner 15 Mar '11

15 Mar '11

Hello! as some of you may already know, i will probably apply for a flashrom (or coreboot) project for this year's gsoc. i am studying computer science or more specifically computer engineering at the technical university in vienna (austria) since 2005 and will hopefully graduate this year :) i have contributed smaller pieces to different oss projects and i am doing regular bug reporting from kernel specific issues to daily annoyances in ubuntu, but i have never been engaged in the cooperative development of a bigger software project for a longer period. please see below for the shortlog of the incoming patches. a forked git tree including all this can be found at https://github.com/stefanct/flashrom i hang around in irc in case there are questions or flames you don't wanna see on the list :) Stefan Tauner (7): whitespace, documentation and other small stuff The AT25F512B is quite different from the other (yet unsupported) chips in the AT25F* familiy, so rename 512B-specific stuff. generify spi_rdid to allow passing different opcodes. This is needed to add support for Atmel's AT25F series. Add support for Atmel's AT25F series of SPI flash chips. This includes a new probing method (probe_spi_rdid_at25f), block erase method (spi_block_erase_62), spi_prettyprint_status_register_at25f and spi_disable_blockprotect_at25f. add support for 8086:1076 (82541GI) to nicintel_spi.c use getpagesize() to determine physmap's length in nicintel_spi.c check if write enable is really set in nicintel_spi_init (and minor comment changes). chipdrivers.h | 3 + chipset_enable.c | 4 +- drkaiser.c | 2 +- flash.h | 7 ++- flashchips.c | 89 +++++++++++++++++++++++++++ flashchips.h | 14 ++--- flashrom.c | 4 +- nicintel_spi.c | 23 ++++++- print.c | 2 +- print_wiki.c | 2 +- spi.h | 14 +++- spi25.c | 177 ++++++++++++++++++++++++++++++++++++++++++++++------- wbsio_spi.c | 2 +- 13 files changed, 294 insertions(+), 49 deletions(-)

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