February 2016 - flashrom - mail.coreboot.org

Re: [flashrom] New programmer board "SPI_TT LPT" support - patch submission
by Stefan Tauner Feb. 28, 2016

Feb. 28, 2016

On Sun, 28 Feb 2016 22:17:32 +0300 Max <flammaden(a)gmail.com> wrote: > The circuit power is totally on ham choice. Usually, 5V from USB or PC PSU > molex and LDO for 3.3V + some cap ~10mF after it. Everything's clear now, thanks. > If previous image is copyrighted, I have another one. :) > If you did not draw it yourself or the author gave his permission in form of an appropriate license you are not allowed to publish *any* picture - and we are not allowed to host them for the public in our mailing list archive either... -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] New programmer board "SPI_TT LPT" support - patch submission
by Stefan Tauner Feb. 28, 2016

Feb. 28, 2016

On Sun, 28 Feb 2016 15:27:09 +0300 Max <flammaden(a)gmail.com> wrote: > SPI read was tested. Write wasn't, because of sudden AC voltage blackout > and I haven't had any more effort going to collecting build tools and > struggling with build process. > It's buffer enable pin is hardwired, so no control required. Ok, thanks! I have committed a variation of your patch in r1945 but left the status as untested. > > In attachment there are SPI-TT schematics, so you can add it to man page. That's easily discoverable (and copyrighted) so we won't include it. However, I was not able to find out how the circuit is powered (most information sources are in russian and translating them automatically was not enough to find out :). I presume Vcc is connected to an external power source, right? -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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[commit] r1945 - trunk
by repository service Feb. 28, 2016

Feb. 28, 2016

Author: stefanct Date: Sun Feb 28 18:04:38 2016 New Revision: 1945 URL: http://flashrom.org/trac/flashrom/changeset/1945 Log: rayer_spi: add support for SPI Tiny Tools-compatible hardware. Apparently, there is at least one board of Russian origin (coined SPI_TT LPT) that works with SPI Tiny Tools which is a closed-source Windows GUI program somewhat similar to flashrom. Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Modified: trunk/flashrom.8.tmpl trunk/rayer_spi.c Modified: trunk/flashrom.8.tmpl ============================================================================== --- trunk/flashrom.8.tmpl Sat Feb 27 00:51:21 2016 (r1944) +++ trunk/flashrom.8.tmpl Sun Feb 28 18:04:38 2016 (r1945) @@ -899,7 +899,8 @@ .B model can be .BR rayer " for the RayeR cable, " byteblastermv " for the Altera ByteBlasterMV, " stk200 " for the Atmel \ -STK200/300, " wiggler " for the Macraigor Wiggler, or " xilinx " for the Xilinx Parallel Cable III (DLC 5)." +STK200/300, " wiggler " for the Macraigor Wiggler, " xilinx " for the Xilinx Parallel Cable III (DLC 5), or" \ +" spi_tt" " for SPI Tiny Tools-compatible hardware. .sp More information about the RayeR hardware is available at .nh Modified: trunk/rayer_spi.c ============================================================================== --- trunk/rayer_spi.c Sat Feb 27 00:51:21 2016 (r1944) +++ trunk/rayer_spi.c Sun Feb 28 18:04:38 2016 (r1945) @@ -106,12 +106,20 @@ .miso_bit = 7, }; +static const struct rayer_pinout spi_tt = { + .cs_bit = 2, + .sck_bit = 0, + .mosi_bit = 4, + .miso_bit = 7, +}; + static const struct rayer_programmer rayer_spi_types[] = { {"rayer", NT, "RayeR SPIPGM", &rayer_spipgm}, {"xilinx", NT, "Xilinx Parallel Cable III (DLC 5)", &xilinx_dlc5}, {"byteblastermv", OK, "Altera ByteBlasterMV", &altera_byteblastermv}, {"stk200", NT, "Atmel STK200/300 adapter", &atmel_stk200}, {"wiggler", OK, "Wiggler LPT", &wiggler_lpt}, + {"spi_tt", NT, "SPI Tiny Tools (SPI_TT LPT)", &spi_tt}, {0}, };

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Re: [flashrom] New programmer board "SPI_TT LPT" support - patch submission
by Stefan Tauner Feb. 28, 2016

Feb. 28, 2016

On Sun, 28 Feb 2016 11:03:19 +0300 Max <flammaden(a)gmail.com> wrote: > Hello, Stefan! > > Actually, I doesn't real Linux C programmer - I just passed by. :) > So, I just tried to get into this area, but get very distracted by > wretchedness and inconvenience of Linux development tools. I don't think > there's will be next time. :) I just "threw patch away", hoping that this > programmer widely enough available and somebody, having proper skills, > finishes it. Seems to be, my thoughts was wrong, but till now I don't be > sad. > Now I surprised! Thank you for your precious time to finish this patch, > Stefan! > > I marked them as untested because I think that my one working quick dirty > patch is not an reliable proof of testing. The patch alone is no proof but if you have tested it with real hardware and it worked then there is no reason to not believe you and mark it as tested. Have you run flashrom with your patch on that hardware and did writing work? > It doesn't need any enable routine - it has no logic, no triggers/relay - > just resistors and buffer. Buffers most often have disable (or enable) pins and if they are not pulled down (or up) statically by resistors we need to do that dynamically when starting to access the programmer. This would not be unusual at all for this class of programmers... hence my question. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] New programmer board "SPI_TT LPT" support - patch submission
by Stefan Tauner Feb. 28, 2016

Feb. 28, 2016

On Tue, 4 Aug 2015 11:12:08 +0300 Max <flammaden(a)gmail.com> wrote: > Hello, everybody, involved into flashrom! > > I'd implemented support for well known in Russia SPI_TT LPT programmer. > Basically, it's only Byteblaster clone with changed pinout. So, > modifications was pretty straIghtforward. > > In attach - modified "rayer_spi.c" from trunk branch. > Hope, it will be useful for someone. Hi Max, thanks for your contribution! Please post a proper patch according to our development guidelines next time: https://www.flashrom.org/Development_Guidelines I have prepared a patch as you suggested and even included an entry to the manpage. However, I wonder if you have tested your file successfully because the tested field was set to NT instead of OK. Also, doesn't it need any enable routine like the byteblaster? -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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[PATCH] Add support for GD25VQ21B, GD25VQ40C, GD25VQ80C and GD25VQ16C
by Hatim Kanchwala Feb. 28, 2016

Feb. 28, 2016

Signed-off-by: Hatim Kanchwala <hatim(a)hatimak.me> --- flashchips.c | 163 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ flashchips.h | 5 +- 2 files changed, 167 insertions(+), 1 deletion(-) diff --git a/flashchips.c b/flashchips.c index 238389b..eb6eacb 100644 --- a/flashchips.c +++ b/flashchips.c @@ -6285,26 +6285,66 @@ const struct flashchip flashchips[] = { .eraseblocks = { {1024 * 1024, 1} }, .block_erase = spi_block_erase_c7, } }, .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, .voltage = {2700, 3600}, }, { .vendor = "GigaDevice", + .name = "GD25VQ21B", + .bustype = BUS_SPI, + .manufacture_id = GIGADEVICE_ID, + .model_id = GIGADEVICE_GD25VQ21B, + .total_size = 256, + .page_size = 256, + /* OTP: 1536B total; read 0x48, write 0x42, erase 0x44 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { { 4 * 1024, 64} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { { 32 * 1024, 8} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { { 64 * 1024, 4} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {256 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {256 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + /* TODO: 2nd Status Register; read 0x35 */ + .printlock = spi_prettyprint_status_register_bp4_srwd, + .unlock = spi_disable_blockprotect_bp4_srwd, + .write = spi_chip_write_256, + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {2300, 3600}, + }, + + { + .vendor = "GigaDevice", .name = "GD25VQ41B", .bustype = BUS_SPI, .manufacture_id = GIGADEVICE_ID, .model_id = GIGADEVICE_GD25VQ41B, .total_size = 512, .page_size = 256, /* OTP: 1536B total; read 0x48, write 0x42, erase 0x44 */ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = { @@ -6324,26 +6364,149 @@ const struct flashchip flashchips[] = { .eraseblocks = { {512 * 1024, 1} }, .block_erase = spi_block_erase_c7, } }, /* TODO: 2nd Status Register; read 0x35 */ .printlock = spi_prettyprint_status_register_bp4_srwd, .unlock = spi_disable_blockprotect_bp4_srwd, .write = spi_chip_write_256, .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {2300, 3600}, }, { + .vendor = "GigaDevice", + .name = "GD25VQ40C", + .bustype = BUS_SPI, + .manufacture_id = GIGADEVICE_ID, + .model_id = GIGADEVICE_GD25VQ41B, + .total_size = 512, + .page_size = 256, + /* Supports SFDP; read 0x5A */ + /* OTP: 1024B total; read 0x48, write 0x42, erase 0x44 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { { 4 * 1024, 128} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { { 32 * 1024, 16} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { { 64 * 1024, 8} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + /* TODO: 2nd Status Register; read 0x35 */ + .printlock = spi_prettyprint_status_register_bp4_srwd, + .unlock = spi_disable_blockprotect_bp4_srwd, + .write = spi_chip_write_256, + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {2300, 3600}, + }, + + { + .vendor = "GigaDevice", + .name = "GD25VQ80C", + .bustype = BUS_SPI, + .manufacture_id = GIGADEVICE_ID, + .model_id = GIGADEVICE_GD25VQ80C, + .total_size = 1024, + .page_size = 256, + /* Supports SFDP; read 0x5A */ + /* OTP: 1024B total; read 0x48, write 0x42, erase 0x44 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { { 4 * 1024, 256} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { { 32 * 1024, 32} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { { 64 * 1024, 16} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + /* TODO: 2nd Status Register; read 0x35 */ + .printlock = spi_prettyprint_status_register_bp4_srwd, + .unlock = spi_disable_blockprotect_bp4_srwd, + .write = spi_chip_write_256, + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {2300, 3600}, + }, + + { + .vendor = "GigaDevice", + .name = "GD25VQ16C", + .bustype = BUS_SPI, + .manufacture_id = GIGADEVICE_ID, + .model_id = GIGADEVICE_GD25VQ16C, + .total_size = 2 * 1024, + .page_size = 256, + /* Supports SFDP; read 0x5A */ + /* OTP: 1024B total; read 0x48, write 0x42, erase 0x44 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { { 4 * 1024, 512} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { { 32 * 1024, 64} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { { 64 * 1024, 32} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {2 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {2 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + /* TODO: 2nd Status Register; read 0x35 */ + .printlock = spi_prettyprint_status_register_bp4_srwd, + .unlock = spi_disable_blockprotect_bp4_srwd, + .write = spi_chip_write_256, + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {2300, 3600}, + }, + + { .vendor = "Hyundai", .name = "HY29F002T", .bustype = BUS_PARALLEL, .manufacture_id = HYUNDAI_ID, .model_id = HYUNDAI_HY29F002T, .total_size = 256, .page_size = 256 * 1024, .feature_bits = FEATURE_EITHER_RESET, /* Some revisions may need FEATURE_ADDR_2AA */ .tested = TEST_OK_PRE, .probe = probe_jedec, .probe_timing = TIMING_ZERO, /* Datasheet has no timing info specified */ .block_erasers = { diff --git a/flashchips.h b/flashchips.h index a109e94..ac1901f 100644 --- a/flashchips.h +++ b/flashchips.h @@ -368,27 +368,30 @@ #define GIGADEVICE_GD25Q20 0x4012 /* Same as GD25QB */ #define GIGADEVICE_GD25Q40 0x4013 /* Same as GD25QB */ #define GIGADEVICE_GD25Q80 0x4014 /* Same as GD25Q80B (which has OTP) */ #define GIGADEVICE_GD25Q16 0x4015 /* Same as GD25Q16B (which has OTP) */ #define GIGADEVICE_GD25Q32 0x4016 /* Same as GD25Q32B */ #define GIGADEVICE_GD25Q64 0x4017 /* Same as GD25Q64B */ #define GIGADEVICE_GD25Q128 0x4018 /* GD25Q128B and GD25Q128C only, can be distinguished by SFDP */ #define GIGADEVICE_GD25LQ40 0x6013 #define GIGADEVICE_GD25LQ80 0x6014 #define GIGADEVICE_GD25LQ16 0x6015 #define GIGADEVICE_GD25LQ32 0x6016 #define GIGADEVICE_GD25LQ64 0x6017 /* Same as GD25LQ64B (which is faster) */ #define GIGADEVICE_GD25LQ128 0x6018 -#define GIGADEVICE_GD25VQ41B 0x4213 +#define GIGADEVICE_GD25VQ21B 0x4212 +#define GIGADEVICE_GD25VQ41B 0x4213 /* Same as GD25VQ40C, can be distinguished by SFDP */ +#define GIGADEVICE_GD25VQ80C 0x4214 +#define GIGADEVICE_GD25VQ16C 0x4215 #define GIGADEVICE_GD29GL064CAB 0x7E0601 #define HYUNDAI_ID 0xAD /* Hyundai */ #define HYUNDAI_HY29F400T 0x23 /* Same as HY29F400AT */ #define HYUNDAI_HY29F800B 0x58 /* Same as HY29F800AB */ #define HYUNDAI_HY29LV800B 0x5B #define HYUNDAI_HY29F040A 0xA4 #define HYUNDAI_HY29F400B 0xAB /* Same as HY29F400AB */ #define HYUNDAI_HY29F002B 0x34 #define HYUNDAI_HY29F002T 0xB0 #define HYUNDAI_HY29LV400T 0xB9 #define HYUNDAI_HY29LV400B 0xBA #define HYUNDAI_HY29F080 0xD5 -- Regards, Hatim Kanchwala http://hatimak.me B. Tech. Electrical Engineering Indian Institute of Technology Patna

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[PATCH] ch341a_spi: provide nACT/ACT with CS1/2 for ISP use
by Urja Rannikko Feb. 28, 2016

Feb. 28, 2016

This allows to drive MCU RST lines or similar with the ch341a during a flashrom run. CS1 is active low and CS2 is active high; note that the tristate state is a weak pullup, thus using CS2 would need an external pull-down. Signed-off-by: Urja Rannikko <urjaman(a)gmail.com> --- ch341a_spi.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/ch341a_spi.c b/ch341a_spi.c index 6eb2804..7e5d577 100644 --- a/ch341a_spi.c +++ b/ch341a_spi.c @@ -303,8 +303,12 @@ static uint8_t swap_byte(uint8_t x) static int32_t enable_pins(bool enable) { uint8_t buf[] = { + /* We provide CS1 as "nACT" and CS2 as "ACT" during operation for ISP + * designs to drive eg. reset lines, meaning CS1 is driven low during + * flashrom run and CS2 high. Note that the tristate state is a weak + * pullup, thus using CS2 needs an external pull-down. */ CH341A_CMD_UIO_STREAM, - CH341A_CMD_UIO_STM_OUT | 0x37, // CS high (all of them), SCK=0, DOUT*=1 + CH341A_CMD_UIO_STM_OUT | (enable ? 0x35 : 0x33), // SCK=0, DOUT*=1 CH341A_CMD_UIO_STM_DIR | (enable ? 0x3F : 0x00), // Interface output enable / disable CH341A_CMD_UIO_STM_END, }; @@ -327,11 +331,11 @@ static void pluck_cs(uint8_t *ptr) stored_delay_us = 0; } *ptr++ = CH341A_CMD_UIO_STREAM; - *ptr++ = CH341A_CMD_UIO_STM_OUT | 0x37; /* deasserted */ + *ptr++ = CH341A_CMD_UIO_STM_OUT | 0x35; /* deasserted */ int i; for (i = 0; i < delay_cnt; i++) - *ptr++ = CH341A_CMD_UIO_STM_OUT | 0x37; /* "delay" */ - *ptr++ = CH341A_CMD_UIO_STM_OUT | 0x36; /* asserted */ + *ptr++ = CH341A_CMD_UIO_STM_OUT | 0x35; /* "delay" */ + *ptr++ = CH341A_CMD_UIO_STM_OUT | 0x34; /* asserted */ *ptr++ = CH341A_CMD_UIO_STM_END; } -- 2.7.1

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Re: [flashrom] [PATCH] Drop non-existing support for nicnatsemi.
by Carl-Daniel Hailfinger Feb. 27, 2016

Feb. 27, 2016

On 27.02.2016 17:07, Stefan Tauner wrote: > This was meant to support National Semiconductor DP838* network cards > but was never tested successfully. The hardware does not seem to be > available on the market anymore and there was no development for > five years. > > Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Nack, I'd like to push it to some "request for help" section on flashrom.org to find out if someone or some hackerspace has the hardware and is willing to get this finalized. Regards, Carl-Daniel

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[PATCH] Drop non-existing support for nicnatsemi.
by Stefan Tauner Feb. 27, 2016

Feb. 27, 2016

This was meant to support National Semiconductor DP838* network cards but was never tested successfully. The hardware does not seem to be available on the market anymore and there was no development for five years. Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> --- Makefile | 24 ------------ flashrom.8.tmpl | 9 ++--- flashrom.c | 12 ------ nicnatsemi.c | 115 -------------------------------------------------------- programmer.h | 9 ----- 5 files changed, 3 insertions(+), 166 deletions(-) delete mode 100644 nicnatsemi.c diff --git a/Makefile b/Makefile index 1511eef..7b7d666 100644 --- a/Makefile +++ b/Makefile @@ -249,11 +249,6 @@ UNSUPPORTED_FEATURES += CONFIG_NICREALTEK=yes else override CONFIG_NICREALTEK = no endif -ifeq ($(CONFIG_NICNATSEMI), yes) -UNSUPPORTED_FEATURES += CONFIG_NICNATSEMI=yes -else -override CONFIG_NICNATSEMI = no -endif ifeq ($(CONFIG_NICINTEL), yes) UNSUPPORTED_FEATURES += CONFIG_NICINTEL=yes else @@ -387,11 +382,6 @@ UNSUPPORTED_FEATURES += CONFIG_NICREALTEK=yes else override CONFIG_NICREALTEK = no endif -ifeq ($(CONFIG_NICNATSEMI), yes) -UNSUPPORTED_FEATURES += CONFIG_NICNATSEMI=yes -else -override CONFIG_NICNATSEMI = no -endif ifeq ($(CONFIG_RAYER_SPI), yes) UNSUPPORTED_FEATURES += CONFIG_RAYER_SPI=yes else @@ -478,11 +468,6 @@ UNSUPPORTED_FEATURES += CONFIG_NICREALTEK=yes else override CONFIG_NICREALTEK = no endif -ifeq ($(CONFIG_NICNATSEMI), yes) -UNSUPPORTED_FEATURES += CONFIG_NICNATSEMI=yes -else -override CONFIG_NICNATSEMI = no -endif ifeq ($(CONFIG_NICINTEL), yes) UNSUPPORTED_FEATURES += CONFIG_NICINTEL=yes else @@ -606,9 +591,6 @@ CONFIG_DRKAISER ?= yes # Always enable Realtek NICs for now. CONFIG_NICREALTEK ?= yes -# Disable National Semiconductor NICs until support is complete and tested. -CONFIG_NICNATSEMI ?= no - # Always enable Intel NICs for now. CONFIG_NICINTEL ?= yes @@ -860,12 +842,6 @@ PROGRAMMER_OBJS += nicrealtek.o NEED_LIBPCI += CONFIG_NICREALTEK endif -ifeq ($(CONFIG_NICNATSEMI), yes) -FEATURE_CFLAGS += -D'CONFIG_NICNATSEMI=1' -PROGRAMMER_OBJS += nicnatsemi.o -NEED_LIBPCI += CONFIG_NICNATSEMI -endif - ifeq ($(CONFIG_NICINTEL), yes) FEATURE_CFLAGS += -D'CONFIG_NICINTEL=1' PROGRAMMER_OBJS += nicintel.o diff --git a/flashrom.8.tmpl b/flashrom.8.tmpl index 9d8fcc3..2c68351 100644 --- a/flashrom.8.tmpl +++ b/flashrom.8.tmpl @@ -216,9 +216,6 @@ involving any chip access (probe/read/write/...). Currently supported are: .sp .BR "* nicrealtek" " (for flash ROMs on Realtek and SMC 1211 network cards)" .sp -.BR "* nicnatsemi" " (for flash ROMs on National Semiconductor DP838* network \ -cards)" -.sp .BR "* nicintel" " (for parallel flash ROMs on Intel 10/100Mbit network cards) .sp .BR "* gfxnvidia" " (for flash ROMs on NVIDIA graphics cards)" @@ -638,7 +635,7 @@ syntax where .B content is an 8-bit hexadecimal value. .SS -.BR "nic3com" , " nicrealtek" , " nicnatsemi" , " nicintel", " nicintel_eeprom"\ +.BR "nic3com" , " nicrealtek" , " nicintel", " nicintel_eeprom"\ , " nicintel_spi" , " gfxnvidia" , " ogp_spi" , " drkaiser" , " satasii"\ , " satamv" , " atahpt", " atavia ", " atapromise " and " it8212 " programmers .IP @@ -1057,7 +1054,7 @@ access (x86) and MSR access (x86). .B atavia needs PCI configuration space access. .sp -.BR nic3com ", " nicrealtek " and " nicnatsemi " +.BR nic3com " and " nicnatsemi " need PCI configuration space read access and raw I/O port access. .sp .B atahpt @@ -1091,7 +1088,7 @@ need access to the respective USB device via libusb API version 1.0. .B dummy needs no access permissions at all. .sp -.BR internal ", " nic3com ", " nicrealtek ", " nicnatsemi ", " +.BR internal ", " nic3com ", " nicrealtek ", " .BR gfxnvidia ", " drkaiser ", " satasii ", " satamv ", " atahpt ", " atavia " and " atapromise have to be run as superuser/root, and need additional raw access permission. .sp diff --git a/flashrom.c b/flashrom.c index 25e53f2..92e7abc 100644 --- a/flashrom.c +++ b/flashrom.c @@ -110,18 +110,6 @@ const struct programmer_entry programmer_table[] = { }, #endif -#if CONFIG_NICNATSEMI == 1 - { - .name = "nicnatsemi", - .type = PCI, - .devs.dev = nics_natsemi, - .init = nicnatsemi_init, - .map_flash_region = fallback_map, - .unmap_flash_region = fallback_unmap, - .delay = internal_delay, - }, -#endif - #if CONFIG_GFXNVIDIA == 1 { .name = "gfxnvidia", diff --git a/nicnatsemi.c b/nicnatsemi.c deleted file mode 100644 index ce22c94..0000000 --- a/nicnatsemi.c +++ /dev/null @@ -1,115 +0,0 @@ -/* - * This file is part of the flashrom project. - * - * Copyright (C) 2010 Andrew Morgan <ziltro(a)ziltro.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#if defined(__i386__) || defined(__x86_64__) - -#include <stdlib.h> -#include "flash.h" -#include "programmer.h" -#include "hwaccess.h" - -#define PCI_VENDOR_ID_NATSEMI 0x100b - -#define BOOT_ROM_ADDR 0x50 -#define BOOT_ROM_DATA 0x54 - -static uint32_t io_base_addr = 0; -const struct dev_entry nics_natsemi[] = { - {0x100b, 0x0020, NT, "National Semiconductor", "DP83815/DP83816"}, - {0x100b, 0x0022, NT, "National Semiconductor", "DP83820"}, - - {0}, -}; - -static void nicnatsemi_chip_writeb(const struct flashctx *flash, uint8_t val, - chipaddr addr); -static uint8_t nicnatsemi_chip_readb(const struct flashctx *flash, - const chipaddr addr); -static const struct par_master par_master_nicnatsemi = { - .chip_readb = nicnatsemi_chip_readb, - .chip_readw = fallback_chip_readw, - .chip_readl = fallback_chip_readl, - .chip_readn = fallback_chip_readn, - .chip_writeb = nicnatsemi_chip_writeb, - .chip_writew = fallback_chip_writew, - .chip_writel = fallback_chip_writel, - .chip_writen = fallback_chip_writen, -}; - -int nicnatsemi_init(void) -{ - struct pci_dev *dev = NULL; - - if (rget_io_perms()) - return 1; - - dev = pcidev_init(nics_natsemi, PCI_BASE_ADDRESS_0); - if (!dev) - return 1; - - io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0); - if (!io_base_addr) - return 1; - - /* The datasheet shows address lines MA0-MA16 in one place and MA0-MA15 - * in another. My NIC has MA16 connected to A16 on the boot ROM socket - * so I'm assuming it is accessible. If not then next line wants to be - * max_rom_decode.parallel = 65536; and the mask in the read/write - * functions below wants to be 0x0000FFFF. - */ - max_rom_decode.parallel = 131072; - register_par_master(&par_master_nicnatsemi, BUS_PARALLEL); - - return 0; -} - -static void nicnatsemi_chip_writeb(const struct flashctx *flash, uint8_t val, - chipaddr addr) -{ - OUTL((uint32_t)addr & 0x0001FFFF, io_base_addr + BOOT_ROM_ADDR); - /* - * The datasheet requires 32 bit accesses to this register, but it seems - * that requirement might only apply if the register is memory mapped. - * Bits 8-31 of this register are apparently don't care, and if this - * register is I/O port mapped, 8 bit accesses to the lowest byte of the - * register seem to work fine. Due to that, we ignore the advice in the - * data sheet. - */ - OUTB(val, io_base_addr + BOOT_ROM_DATA); -} - -static uint8_t nicnatsemi_chip_readb(const struct flashctx *flash, - const chipaddr addr) -{ - OUTL(((uint32_t)addr & 0x0001FFFF), io_base_addr + BOOT_ROM_ADDR); - /* - * The datasheet requires 32 bit accesses to this register, but it seems - * that requirement might only apply if the register is memory mapped. - * Bits 8-31 of this register are apparently don't care, and if this - * register is I/O port mapped, 8 bit accesses to the lowest byte of the - * register seem to work fine. Due to that, we ignore the advice in the - * data sheet. - */ - return INB(io_base_addr + BOOT_ROM_DATA); -} - -#else -#error PCI port I/O access is not supported on this architecture yet. -#endif diff --git a/programmer.h b/programmer.h index bd8e98d..c031ff7 100644 --- a/programmer.h +++ b/programmer.h @@ -39,9 +39,6 @@ enum programmer { #if CONFIG_NICREALTEK == 1 PROGRAMMER_NICREALTEK, #endif -#if CONFIG_NICNATSEMI == 1 - PROGRAMMER_NICNATSEMI, -#endif #if CONFIG_GFXNVIDIA == 1 PROGRAMMER_GFXNVIDIA, #endif @@ -411,12 +408,6 @@ int nicrealtek_init(void); extern const struct dev_entry nics_realtek[]; #endif -/* nicnatsemi.c */ -#if CONFIG_NICNATSEMI == 1 -int nicnatsemi_init(void); -extern const struct dev_entry nics_natsemi[]; -#endif - /* nicintel.c */ #if CONFIG_NICINTEL == 1 int nicintel_init(void); -- Kind regards, Stefan Tauner

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Re: [flashrom] [PATCH] Add support for GD25VQ21B, GD25VQ40C, GD25VQ80C and GD25VQ16C
by Stefan Tauner Feb. 27, 2016

Feb. 27, 2016

On Fri, 26 Feb 2016 15:52:40 -0800 David Hendricks <dhendrix(a)google.com> wrote: > > +#define GIGADEVICE_GD25VQ21B 0x4212 > > +#define GIGADEVICE_GD25VQ41B 0x4213 /* Same as GD25VQ40C, can be distinguished by SFDP */ > This comment should go in the .c file, above the model_id for the > GD25VQ40C and GD25VQ41B. The only real reason for having flashchips.h is having a nice overview of IDs and relevant information thus that comment is perfectly fine there - it would get lost in the shuffle in the .c file. We have lots of similar comments in the .h file, most prominently the one for the GIGADEVICE_GD25Q128 that the above was copied from ;) -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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