flashrom February 2016

flashrom@flashrom.org

26 participants
96 discussions

Re: [flashrom] [PATCH 3/3] Add support for WCH CH341A as an SPI programmer.
by Stefan Tauner 14 Feb '16

14 Feb '16

On Wed, 27 Jan 2016 03:12:11 +0200 Urja Rannikko <urjaman(a)gmail.com> wrote: > Hi, > > Review-ish... with some only-commentary included too. > > On Mon, Jan 18, 2016 at 1:28 AM, Stefan Tauner > <stefan.tauner(a)alumni.tuwien.ac.at> wrote: > > Signed-off-by: Urja Rannikko <urjaman(a)gmail.com> > > Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> > > --- > > Makefile | 23 ++- > > ch341a_spi.c | 531 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > > flashrom.8.tmpl | 12 +- > > flashrom.c | 12 ++ > > programmer.h | 13 ++ > > 5 files changed, 588 insertions(+), 3 deletions(-) > > create mode 100644 ch341a_spi.c > > > > + free_idx = (free_idx + 1) % USB_IN_TRANSFERS; /* Increment (and wrap around). */ > Yeah this obvious construct is something I didnt use because I'm such > an embedded guy that I'd never ever use % in performance related > code... (i think i had some if idx>=USB_IN_TRANSFERS) idx = 0 > thing)... thanks for making it saner. :) > I had a fancier delay implementation done (all the way upto ms scale > using the I2C commands), but since i didnt get that fully tested, this > one will do, i'll post it as an improvement later. Please do. I don't deem it that important but since you have investigated the whole issue in such detail it would be a waste to not exploit this knowledge. > > + unsigned int i; > > + for (i = 0; i < readcnt; i++) { > > + /* FIXME: does working on words instead of bytes improve speed? */ > ... drop the comment? i dont really care, but i think our consensus on > IRC was that a words-wide implementation would have more issues > (alignment and such) than performance. > Or make a comment with that info. It's gone. > > + *readarr++ = swap_byte(rbuf[writecnt + i]); > > + } > > + > > + return 0; > > +} > > + > > +static const struct spi_master spi_master_ch341a_spi = { > > + .type = SPI_CONTROLLER_CH341A_SPI, > > + /* TODO: flashrom's current maximum is 256 B. Device was tested on Linux to accept atleast 16 kB. */ > > + .max_data_read = 16 * 1024, > > + .max_data_write = 16 * 1024, > On linux. Not on windows usb "stack" i think... set these back to 1k? > Or test for the limit (maybe something like 4k?) and change the 1000ms > timeout, since i think the big packet would timeout on windows if > nothing else failed... As discussed, I have tested up to 128 kB on Windows (in VM) and on Linux with a bigger timeout and it works fine. We have agreed upon 4 kB chunks now and using VLAs (I had an intermediate version that used bigger chunks and relied on mallocs for them). > With atleast the limits dropped (or tested), this is: > Acked-by: Urja Rannikko <urjaman(a)gmail.com> Thanks, r1921. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] [REVIEW] Add support for google servo board
by Stefan Tauner 14 Feb '16

14 Feb '16

On Sat, 13 Feb 2016 14:34:56 +0200 Urja Rannikko <urjaman(a)gmail.com> wrote: > Hi, > > So Stefan noted that there was something missing, namely man page > entries for the added parameters to ft2232_spi - > hatim helped out with them a little and i finished that part: > > https://github.com/urjaman/flashrom/commit/89bb8a87ca67a27d9a544579f4e4f63b… > > On Sat, Feb 13, 2016 at 1:00 PM, Hatim Kanchwala <hatim(a)hatimak.me> wrote: > > Hello, > > > > Here's the pull request https://github.com/stefanct/flashrom/pull/6 from Alex. It compiles perfectly against the most recent master (as of typing this :p). It looks fine. I had help from Urja reviewing it (although there wasn't much to review in this almost perfect patch ;)). > > > > Acked-by: Hatim Kanchwala <hatim(a)hatimak.me> > With that included, this series is: > Acked-by: Urja Rannikko <urjaman(a)gmail.com> Merged together and committed in r1925, thanks. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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[commit] r1925 - in trunk: . util
by repository service 14 Feb '16

14 Feb '16

Author: stefanct Date: Sun Feb 14 16:46:00 2016 New Revision: 1925 URL: http://flashrom.org/trac/flashrom/changeset/1925 Log: ft2232_spi: Add support for Google Servo boards (v1 + v2). This patch has been cherry-picked from various patches in the chromiumos tree denoted below. Change-Id: I4b679e23ab37a4357b1e3d23f6f65a1c31f7d71a Change-Id: Ibda56201ab4519315431c08206c61ceffb7c7e65 Change-Id: I540ad2d304dc69a7c79ca154beb744ef947ff808 Servo V2 has two FT4232H parts. The first one (denoted 'legacy') is dedicated to supporting orginal Servo V1 functionality. The second, residing at USB ID 0x18d1:5003 provides two other SPI interfaces on port A and B respectively. Additional changes by Alexandru Gagniuc, Hatim Kanchwala and Urja Rannikko: - The clock divisor is set to '6', as this creates a 10MHz SPI clock, which is the same SPI clock that the chromiumos branch produced. - Add udev rule for Google servo boards to util/flashrom.rules. - Add Google servo entry to manpage. Signed-off-by: Todd Broch <tbroch(a)chromium.org> Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Signed-off-by: Hatim Kanchwala <hatim(a)hatimak.me> Signed-off-by: Urja Rannikko <urjaman(a)gmail.com> Acked-by: Hatim Kanchwala <hatim(a)hatimak.me> Acked-by: Urja Rannikko <urjaman(a)gmail.com> Acked-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Modified: trunk/flashrom.8.tmpl trunk/ft2232_spi.c trunk/util/z60_flashrom.rules Modified: trunk/flashrom.8.tmpl ============================================================================== --- trunk/flashrom.8.tmpl Sun Feb 7 04:35:04 2016 (r1924) +++ trunk/flashrom.8.tmpl Sun Feb 14 16:46:00 2016 (r1925) @@ -242,7 +242,7 @@ FTDI FT2232H Mini-Module, FTDI FT4232H Mini-Module, openbiosprog-spi, Amontec \ JTAGkey/JTAGkey-tiny/JTAGkey-2, Dangerous Prototypes Bus Blaster, \ Olimex ARM-USB-TINY/-H, Olimex ARM-USB-OCD/-H, TIAO/DIYGADGET USB -Multi-Protocol Adapter (TUMPA), TUMPA Lite, and GOEPEL PicoTAP. +Multi-Protocol Adapter (TUMPA), TUMPA Lite, GOEPEL PicoTAP and Google Servo v1/v2. .sp .BR "* serprog" " (for flash ROMs attached to a programmer speaking serprog, \ including Arduino-based devices as well as various programmers by Urja Rannikko, \ @@ -701,7 +701,8 @@ can be .BR 2232H ", " 4232H ", " 232H ", " jtagkey ", " busblaster ", " openmoko ", " \ arm-usb-tiny ", " arm-usb-tiny-h ", " arm-usb-ocd ", " arm-usb-ocd-h \ -", " tumpa ", " tumpalite ", or " picotap +", " tumpa ", " tumpalite ", " picotap ", " google-servo ", " google-servo-v2 \ +" or " google-servo-v2-legacy and .B interface can be Modified: trunk/ft2232_spi.c ============================================================================== --- trunk/ft2232_spi.c Sun Feb 7 04:35:04 2016 (r1924) +++ trunk/ft2232_spi.c Sun Feb 14 16:46:00 2016 (r1925) @@ -58,6 +58,11 @@ #define OLIMEX_ARM_OCD_H_PID 0x002B #define OLIMEX_ARM_TINY_H_PID 0x002A +#define GOOGLE_VID 0x18D1 +#define GOOGLE_SERVO_PID 0x5001 +#define GOOGLE_SERVO_V2_PID0 0x5002 +#define GOOGLE_SERVO_V2_PID1 0x5003 + const struct dev_entry devs_ft2232spi[] = { {FTDI_VID, FTDI_FT2232H_PID, OK, "FTDI", "FT2232H"}, {FTDI_VID, FTDI_FT4232H_PID, OK, "FTDI", "FT4232H"}, @@ -66,6 +71,9 @@ {FTDI_VID, TIAO_TUMPA_LITE_PID, OK, "TIAO", "USB Multi-Protocol Adapter Lite"}, {FTDI_VID, AMONTEC_JTAGKEY_PID, OK, "Amontec", "JTAGkey"}, {GOEPEL_VID, GOEPEL_PICOTAP_PID, OK, "GOEPEL", "PicoTAP"}, + {GOOGLE_VID, GOOGLE_SERVO_PID, OK, "Google", "Servo"}, + {GOOGLE_VID, GOOGLE_SERVO_V2_PID0, OK, "Google", "Servo V2 Legacy"}, + {GOOGLE_VID, GOOGLE_SERVO_V2_PID1, OK, "Google", "Servo V2"}, {FIC_VID, OPENMOKO_DBGBOARD_PID, OK, "FIC", "OpenMoko Neo1973 Debug board (V2+)"}, {OLIMEX_VID, OLIMEX_ARM_OCD_PID, OK, "Olimex", "ARM-USB-OCD"}, {OLIMEX_VID, OLIMEX_ARM_TINY_PID, OK, "Olimex", "ARM-USB-TINY"}, @@ -254,6 +262,17 @@ ft2232_vid = OLIMEX_VID; ft2232_type = OLIMEX_ARM_TINY_H_PID; channel_count = 2; + } else if (!strcasecmp(arg, "google-servo")) { + ft2232_vid = GOOGLE_VID; + ft2232_type = GOOGLE_SERVO_PID; + } else if (!strcasecmp(arg, "google-servo-v2")) { + ft2232_vid = GOOGLE_VID; + ft2232_type = GOOGLE_SERVO_V2_PID1; + /* Default divisor is too fast, and chip ID fails */ + divisor = 6; + } else if (!strcasecmp(arg, "google-servo-v2-legacy")) { + ft2232_vid = GOOGLE_VID; + ft2232_type = GOOGLE_SERVO_V2_PID0; } else { msg_perr("Error: Invalid device type specified.\n"); free(arg); Modified: trunk/util/z60_flashrom.rules ============================================================================== --- trunk/util/z60_flashrom.rules Sun Feb 7 04:35:04 2016 (r1924) +++ trunk/util/z60_flashrom.rules Sun Feb 14 16:46:00 2016 (r1925) @@ -60,6 +60,12 @@ # http://www.goepel.com/jtagboundary-scan/hardware/picotap.html ATTRS{idVendor}=="096c", ATTRS{idProduct}=="1449", MODE="664", GROUP="plugdev" +# Google servo debug board +# https://www.chromium.org/chromium-os/servo +ATTRS{idVendor}=="18d1", ATTRS{idProduct}=="5001", MODE="664", GROUP="plugdev" +ATTRS{idVendor}=="18d1", ATTRS{idProduct}=="5002", MODE="664", GROUP="plugdev" +ATTRS{idVendor}=="18d1", ATTRS{idProduct}=="5003", MODE="664", GROUP="plugdev" + # Olimex ARM-USB-OCD # http://olimex.com/dev/arm-usb-ocd.html ATTRS{idVendor}=="15ba", ATTRS{idProduct}=="0003", MODE="664", GROUP="plugdev"

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Flash Rom fails
by Dave Hugh 13 Feb '16

13 Feb '16

Trying to flash my ROM to get a needed Bios update on an APU2B4 from PCENGINES. Booting into a USB tiny core image to perform the flash, get an error message which advises me to email this address. Can you help? Thanks in advance **** Log message ][root@box:/mnt/sdb]$ flashrom -w apu2_160120.rom -p internal flashrom v0.9.7-r1711-APU on Linux 3.8.13-tinycore (i686) flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... delay loop is unreliable, trying to continue OK. coreboot table found at 0xdffae000. Found chipset "AMD FCH". Enabling flash write... FCH device found but SMBus revision 0x42 does not match known values. Please report this to flashrom(a)flashrom.org and include this log and the output of lspci -nnvx, thanks!. OK. FIFO pointer corruption! Pointer is 0, wanted 3 Something else is accessing the flash chip and causes random corruption. Please stop all applications and drivers and IPMI which access the flash chip. No EEPROM/flash device found. Note: flashrom can never write if the flash chip isn't found automatically. **** Command output [][root@box:/mnt/sdb]$ lspci -nnvx 00:00.0 Host bridge [0600]: Advanced Micro Devices [AMD] Device [1022:1566] Subsystem: Advanced Micro Devices [AMD] Device [1022:1566] Flags: bus master, fast devsel, latency 0 00: 22 10 66 15 04 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 66 15 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:02.0 Host bridge [0600]: Advanced Micro Devices [AMD] Device [1022:156b] Flags: fast devsel 00: 22 10 6b 15 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:02.2 PCI bridge [0604]: Advanced Micro Devices [AMD] Device [1022:1439] (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0 Bus: primary=00, secondary=01, subordinate=01, sec-latency=0 I/O behind bridge: 00001000-00001fff Memory behind bridge: fe500000-fe5fffff Capabilities: [50] Power Management version 3 Capabilities: [58] Express Root Port (Slot+), MSI 00 Capabilities: [a0] MSI: Enable+ Count=1/1 Maskable- 64bit+ Capabilities: [b0] Subsystem: Advanced Micro Devices [AMD] Device [1022:1234] Capabilities: [b8] HyperTransport: MSI Mapping Enable+ Fixed+ Capabilities: [100] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?> Kernel driver in use: pcieport 00: 22 10 39 14 07 04 10 00 00 00 04 06 10 00 81 00 10: 00 00 00 00 00 00 00 00 00 01 01 00 11 11 00 00 20: 50 fe 50 fe f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 00 02 03 00 00:02.3 PCI bridge [0604]: Advanced Micro Devices [AMD] Device [1022:1439] (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0 Bus: primary=00, secondary=02, subordinate=02, sec-latency=0 I/O behind bridge: 00002000-00002fff Memory behind bridge: fe600000-fe6fffff Capabilities: [50] Power Management version 3 Capabilities: [58] Express Root Port (Slot+), MSI 00 Capabilities: [a0] MSI: Enable+ Count=1/1 Maskable- 64bit+ Capabilities: [b0] Subsystem: Advanced Micro Devices [AMD] Device [1022:1234] Capabilities: [b8] HyperTransport: MSI Mapping Enable+ Fixed+ Capabilities: [100] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?> Kernel driver in use: pcieport 00: 22 10 39 14 07 04 10 00 00 00 04 06 10 00 81 00 10: 00 00 00 00 00 00 00 00 00 02 02 00 21 21 00 00 20: 60 fe 60 fe f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 00 03 03 00 00:02.4 PCI bridge [0604]: Advanced Micro Devices [AMD] Device [1022:1439] (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0 Bus: primary=00, secondary=03, subordinate=03, sec-latency=0 I/O behind bridge: 00003000-00003fff Memory behind bridge: fe700000-fe7fffff Capabilities: [50] Power Management version 3 Capabilities: [58] Express Root Port (Slot+), MSI 00 Capabilities: [a0] MSI: Enable+ Count=1/1 Maskable- 64bit+ Capabilities: [b0] Subsystem: Advanced Micro Devices [AMD] Device [1022:1234] Capabilities: [b8] HyperTransport: MSI Mapping Enable+ Fixed+ Capabilities: [100] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?> Kernel driver in use: pcieport 00: 22 10 39 14 07 04 10 00 00 00 04 06 10 00 81 00 10: 00 00 00 00 00 00 00 00 00 03 03 00 31 31 00 00 20: 70 fe 70 fe f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 00 04 03 00 00:02.5 PCI bridge [0604]: Advanced Micro Devices [AMD] Device [1022:1439] (prog-if 00 [Normal decode]) Flags: bus master, fast devsel, latency 0 Bus: primary=00, secondary=04, subordinate=04, sec-latency=0 Memory behind bridge: fe800000-fe8fffff Capabilities: [50] Power Management version 3 Capabilities: [58] Express Root Port (Slot+), MSI 00 Capabilities: [a0] MSI: Enable+ Count=1/1 Maskable- 64bit+ Capabilities: [b0] Subsystem: Advanced Micro Devices [AMD] Device [1022:1234] Capabilities: [b8] HyperTransport: MSI Mapping Enable+ Fixed+ Capabilities: [100] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?> Kernel driver in use: pcieport 00: 22 10 39 14 06 04 10 00 00 00 04 06 10 00 81 00 10: 00 00 00 00 00 00 00 00 00 04 04 00 f1 01 00 00 20: 80 fe 80 fe f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 50 00 00 00 00 00 00 00 00 01 03 00 00:08.0 Encryption controller [1080]: Advanced Micro Devices [AMD] Device [1022:1537] Subsystem: Advanced Micro Devices [AMD] Device [1022:1537] Flags: fast devsel Memory at feb00000 (64-bit, prefetchable) [size=128K] Memory at fe900000 (32-bit, non-prefetchable) [size=1M] Memory at feb24000 (32-bit, non-prefetchable) [size=4K] Memory at fea00000 (32-bit, non-prefetchable) [size=1M] Memory at feb20000 (32-bit, non-prefetchable) [size=8K] Capabilities: [50] MSI-X: Enable- Count=2 Masked- Capabilities: [5c] HyperTransport: MSI Mapping Enable+ Fixed+ Capabilities: [60] Power Management version 3 00: 22 10 37 15 02 00 10 00 00 00 80 10 00 00 00 00 10: 0c 00 b0 fe 00 00 00 00 00 00 90 fe 00 40 b2 fe 20: 00 00 a0 fe 00 00 b2 fe 00 00 00 00 22 10 37 15 30: 00 00 00 00 50 00 00 00 00 00 00 00 00 00 00 00 00:10.0 USB Controller [0c03]: Advanced Micro Devices [AMD] Device [1022:7814] (rev 11) (prog-if 30) Subsystem: Advanced Micro Devices [AMD] Device [1022:1410] Flags: bus master, fast devsel, latency 0, IRQ 18 Memory at feb22000 (64-bit, non-prefetchable) [size=8K] Capabilities: [50] Power Management version 3 Capabilities: [70] MSI: Enable- Count=1/8 Maskable- 64bit+ Capabilities: [90] MSI-X: Enable+ Count=8 Masked- Capabilities: [a0] Express Root Complex Integrated Endpoint, MSI 00 Capabilities: [100] #18 Kernel driver in use: xhci_hcd 00: 22 10 14 78 06 04 10 00 11 30 03 0c 10 00 00 00 10: 04 20 b2 fe 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 10 14 30: 00 00 00 00 50 00 00 00 00 00 00 00 00 01 00 00 00:11.0 SATA controller [0106]: Advanced Micro Devices [AMD] Hudson SATA Controller [IDE mode] [1022:7800] (rev 40) (prog-if 01 [AHCI 1.0]) Subsystem: Advanced Micro Devices [AMD] Hudson SATA Controller [IDE mode] [1022:7800] Flags: bus master, 66MHz, medium devsel, latency 64, IRQ 19 I/O ports at 4010 [size=8] I/O ports at 4020 [size=4] I/O ports at 4018 [size=8] I/O ports at 4024 [size=4] I/O ports at 4000 [size=16] Memory at feb25000 (32-bit, non-prefetchable) [size=1K] Capabilities: [60] Power Management version 3 Capabilities: [70] SATA HBA v1.0 Kernel driver in use: ahci 00: 22 10 00 78 07 00 30 02 40 01 06 01 10 40 00 00 10: 11 40 00 00 21 40 00 00 19 40 00 00 25 40 00 00 20: 01 40 00 00 00 50 b2 fe 00 00 00 00 22 10 00 78 30: 00 00 00 00 60 00 00 00 00 00 00 00 00 01 00 00 00:13.0 USB Controller [0c03]: Advanced Micro Devices [AMD] Hudson USB EHCI Controller [1022:7808] (rev 39) (prog-if 20 [EHCI]) Subsystem: Advanced Micro Devices [AMD] Hudson USB EHCI Controller [1022:7808] Flags: bus master, 66MHz, medium devsel, latency 64, IRQ 18 Memory at feb25400 (32-bit, non-prefetchable) [size=256] Capabilities: [c0] Power Management version 2 Capabilities: [e4] Debug port: BAR=1 offset=00e0 Kernel driver in use: ehci-pci 00: 22 10 08 78 16 00 b0 02 39 20 03 0c 10 40 00 00 10: 00 54 b2 fe 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 08 78 30: 00 00 00 00 c0 00 00 00 00 00 00 00 00 01 00 00 00:14.0 SMBus [0c05]: Advanced Micro Devices [AMD] Hudson SMBus Controller [1022:780b] (rev 42) Subsystem: Advanced Micro Devices [AMD] Hudson SMBus Controller [1022:780b] Flags: 66MHz, medium devsel 00: 22 10 0b 78 03 04 20 02 42 00 05 0c 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 0b 78 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:14.3 ISA bridge [0601]: Advanced Micro Devices [AMD] Hudson LPC Bridge [1022:780e] (rev 11) Subsystem: Advanced Micro Devices [AMD] Hudson LPC Bridge [1022:780e] Flags: bus master, 66MHz, medium devsel, latency 0 00: 22 10 0e 78 0f 00 20 02 11 00 01 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 0e 78 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:14.7 SD Host controller [0805]: Advanced Micro Devices [AMD] Device [1022:7813] (rev 01) (prog-if 01) Subsystem: Advanced Micro Devices [AMD] Device [1022:7806] Flags: bus master, 66MHz, medium devsel, latency 71, IRQ 16 Memory at feb25500 (64-bit, non-prefetchable) [size=256] Kernel driver in use: sdhci-pci 00: 22 10 13 78 06 00 20 02 01 01 05 08 10 47 80 00 10: 04 55 b2 fe 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 06 78 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00:18.0 Host bridge [0600]: Advanced Micro Devices [AMD] Device [1022:1580] Flags: fast devsel 00: 22 10 80 15 00 00 10 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.1 Host bridge [0600]: Advanced Micro Devices [AMD] Device [1022:1581] Flags: fast devsel 00: 22 10 81 15 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.2 Host bridge [0600]: Advanced Micro Devices [AMD] Device [1022:1582] Flags: fast devsel 00: 22 10 82 15 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.3 Host bridge [0600]: Advanced Micro Devices [AMD] Device [1022:1583] Flags: fast devsel Capabilities: [f0] Secure device <?> 00: 22 10 83 15 00 00 10 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 f0 00 00 00 00 00 00 00 00 00 00 00 00:18.4 Host bridge [0600]: Advanced Micro Devices [AMD] Device [1022:1584] Flags: fast devsel 00: 22 10 84 15 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.5 Host bridge [0600]: Advanced Micro Devices [AMD] Device [1022:1585] Flags: fast devsel 00: 22 10 85 15 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01:00.0 Ethernet controller [0200]: Intel Corporation Device [8086:157b] (rev 03) Subsystem: Intel Corporation Device [8086:0000] Flags: fast devsel Memory at fe500000 (32-bit, non-prefetchable) [size=128K] I/O ports at 1000 [size=32] Memory at fe520000 (32-bit, non-prefetchable) [size=16K] Capabilities: [40] Power Management version 3 Capabilities: [50] MSI: Enable- Count=1/1 Maskable+ 64bit+ Capabilities: [70] MSI-X: Enable- Count=5 Masked- Capabilities: [a0] Express Endpoint, MSI 00 Capabilities: [100] Advanced Error Reporting Capabilities: [140] Device Serial Number 00-0d-b9-ff-ff-40-80-68 Capabilities: [1a0] #17 00: 86 80 7b 15 03 00 10 00 03 00 00 02 10 00 00 00 10: 00 00 50 fe 00 00 00 00 01 10 00 00 00 00 52 fe 20: 00 00 00 00 00 00 00 00 00 00 00 00 86 80 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 01 00 00 02:00.0 Ethernet controller [0200]: Intel Corporation Device [8086:157b] (rev 03) Subsystem: Intel Corporation Device [8086:0000] Flags: fast devsel Memory at fe600000 (32-bit, non-prefetchable) [size=128K] I/O ports at 2000 [size=32] Memory at fe620000 (32-bit, non-prefetchable) [size=16K] Capabilities: [40] Power Management version 3 Capabilities: [50] MSI: Enable- Count=1/1 Maskable+ 64bit+ Capabilities: [70] MSI-X: Enable- Count=5 Masked- Capabilities: [a0] Express Endpoint, MSI 00 Capabilities: [100] Advanced Error Reporting Capabilities: [140] Device Serial Number 00-0d-b9-ff-ff-40-80-69 Capabilities: [1a0] #17 00: 86 80 7b 15 03 00 10 00 03 00 00 02 10 00 00 00 10: 00 00 60 fe 00 00 00 00 01 20 00 00 00 00 62 fe 20: 00 00 00 00 00 00 00 00 00 00 00 00 86 80 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 01 00 00 03:00.0 Ethernet controller [0200]: Intel Corporation Device [8086:157b] (rev 03) Subsystem: Intel Corporation Device [8086:0000] Flags: fast devsel Memory at fe700000 (32-bit, non-prefetchable) [size=128K] I/O ports at 3000 [size=32] Memory at fe720000 (32-bit, non-prefetchable) [size=16K] Capabilities: [40] Power Management version 3 Capabilities: [50] MSI: Enable- Count=1/1 Maskable+ 64bit+ Capabilities: [70] MSI-X: Enable- Count=5 Masked- Capabilities: [a0] Express Endpoint, MSI 00 Capabilities: [100] Advanced Error Reporting Capabilities: [140] Device Serial Number 00-0d-b9-ff-ff-40-80-6a Capabilities: [1a0] #17 00: 86 80 7b 15 03 00 10 00 03 00 00 02 10 00 00 00 10: 00 00 70 fe 00 00 00 00 01 30 00 00 00 00 72 fe 20: 00 00 00 00 00 00 00 00 00 00 00 00 86 80 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 01 00 00 04:00.0 Network controller [0280]: Atheros Communications Inc. AR928X Wireless Network Adapter (PCI-Express) [168c:002a] (rev 01) Subsystem: Atheros Communications Inc. Device [168c:3099] Flags: fast devsel Memory at fe800000 (64-bit, non-prefetchable) [size=64K] Capabilities: [40] Power Management version 2 Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit- Capabilities: [60] Express Legacy Endpoint, MSI 00 Capabilities: [90] MSI-X: Enable- Count=1 Masked- Capabilities: [100] Advanced Error Reporting Capabilities: [140] Virtual Channel Capabilities: [160] Device Serial Number 00-00-00-00-00-00-00-00 00: 8c 16 2a 00 02 00 10 00 01 00 80 02 10 00 00 00 10: 04 00 80 fe 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 8c 16 99 30 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 01 00 00

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Re: [flashrom] [PATCH] Add support for GigaDevice GD25VQ41B
by Stefan Tauner 13 Feb '16

13 Feb '16

On Sat, 13 Feb 2016 14:38:07 +0200 Urja Rannikko <urjaman(a)gmail.com> wrote: > I had always assumed OTP means it has memory that does 1->0 but not 0->1, > which this technically isnt (it's erasable&writable until locked with > the high status register bit(s), > and then not writable at all). That would have made sense, but I am not sure I always tagged it like that... I am not sure that I made mistakes either. So maybe we should indeed tag it otherwise... but how? -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] [PATCH] Add support for GigaDevice GD25VQ41B
by Stefan Tauner 13 Feb '16

13 Feb '16

On Fri, 12 Feb 2016 12:39:51 +0200 Urja Rannikko <urjaman(a)gmail.com> wrote: > >> + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, > These arent "truly/100%" OTP, but one-time-lockable "security > registers" - the effect is most likely > the same (=if they're used they're most likely locked and that makes > them effectively ROM), so > I'm ok with the FEATURE_OTP, but maybe change the comment, my suggestion: > /* Lockable Security Registers: 3 * 512B pages, read 0x48, write 0x42, > erase 0x44 */ Hm... That is most likely my fault. I think there are quite some other chips where I deliberately added the OTP comment (and flag) in the same form although they are one-time-lock-only. Rationale: I wanted to make any chip with any permanently lockable bits easily recognizable before starting to work on adding support for it. Therefore I think the original comment is the way to go for the time being (no need to resend the patch though, Hatim). -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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[REVIEW] Add support for google servo board
by Hatim Kanchwala 13 Feb '16

13 Feb '16

Hello, Here's the pull request https://github.com/stefanct/flashrom/pull/6 from Alex. It compiles perfectly against the most recent master (as of typing this :p). It looks fine. I had help from Urja reviewing it (although there wasn't much to review in this almost perfect patch ;)). Acked-by: Hatim Kanchwala <hatim(a)hatimak.me> -- Regards, Hatim Kanchwala http://hatimak.me B. Tech. Electrical Engineering Indian Institute of Technology Patna

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[PATCH] Add support for GigaDevice GD25VQ41B
by Hatim Kanchwala 12 Feb '16

12 Feb '16

Signed-off-by: Hatim Kanchwala <hatim(a)hatimak.me> --- flashchips.c | 40 ++++++++++++++++++++++++++++++++++++++++ flashchips.h | 1 + 2 files changed, 41 insertions(+) diff --git a/flashchips.c b/flashchips.c index c60514b..26a8d89 100644 --- a/flashchips.c +++ b/flashchips.c @@ -6246,20 +6246,60 @@ const struct flashchip flashchips[] = { } }, .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, .voltage = {2700, 3600}, }, { + .vendor = "GigaDevice", + .name = "GD25VQ41B", + .bustype = BUS_SPI, + .manufacture_id = GIGADEVICE_ID, + .model_id = GIGADEVICE_GD25VQ41B, + .total_size = 512, + .page_size = 256, + /* OTP: 3 * 512B total; read 0x48, write 0x42, erase 0x44 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { { 4 * 1024, 128} }, + .block_erase = spi_block_erase_20, + }. { + .eraseblocks = { { 32 * 1024, 16} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { { 64 * 1024, 8} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + /* TODO: 2nd Status Register; read 0x35 */ + .printlock = spi_prettyprint_status_register_bp4_srwd, + .unlock = spi_disable_blockprotect_bp4_srwd, + .write = spi_chip_write_256, + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {2300, 3600}, + }, + + { .vendor = "Hyundai", .name = "HY29F002T", .bustype = BUS_PARALLEL, .manufacture_id = HYUNDAI_ID, .model_id = HYUNDAI_HY29F002T, .total_size = 256, .page_size = 256 * 1024, .feature_bits = FEATURE_EITHER_RESET, /* Some revisions may need FEATURE_ADDR_2AA */ .tested = TEST_OK_PRE, .probe = probe_jedec, diff --git a/flashchips.h b/flashchips.h index 74c44a0..e469363 100644 --- a/flashchips.h +++ b/flashchips.h @@ -371,20 +371,21 @@ #define GIGADEVICE_GD25Q16 0x4015 /* Same as GD25Q16B (which has OTP) */ #define GIGADEVICE_GD25Q32 0x4016 /* Same as GD25Q32B */ #define GIGADEVICE_GD25Q64 0x4017 /* Same as GD25Q64B */ #define GIGADEVICE_GD25Q128 0x4018 /* GD25Q128B only? */ #define GIGADEVICE_GD25LQ40 0x6013 #define GIGADEVICE_GD25LQ80 0x6014 #define GIGADEVICE_GD25LQ16 0x6015 #define GIGADEVICE_GD25LQ32 0x6016 #define GIGADEVICE_GD25LQ64 0x6017 /* Same as GD25LQ64B (which is faster) */ #define GIGADEVICE_GD25LQ128 0x6018 +#define GIGADEVICE_GD25VQ41B 0x4213 #define GIGADEVICE_GD29GL064CAB 0x7E0601 #define HYUNDAI_ID 0xAD /* Hyundai */ #define HYUNDAI_HY29F400T 0x23 /* Same as HY29F400AT */ #define HYUNDAI_HY29F800B 0x58 /* Same as HY29F800AB */ #define HYUNDAI_HY29LV800B 0x5B #define HYUNDAI_HY29F040A 0xA4 #define HYUNDAI_HY29F400B 0xAB /* Same as HY29F400AB */ #define HYUNDAI_HY29F002B 0x34 #define HYUNDAI_HY29F002T 0xB0 -- Regards, Hatim Kanchwala http://hatimak.me B. Tech. Electrical Engineering Indian Institute of Technology Patna

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Fwd: Re: Cannot compile flashrom for windows
by Bio 09 Feb '16

09 Feb '16

Hello, Did you get have time to check my last message ? I was wondering if you know why i still get an error on last version when trying to open port B And to make flashrom detect and read/write my flash, i know that i must add my flash into flashchips.c After reading the data sheet of my flash MX25L25635F i understood that the 24 bit address protocol of Flash can only access up to 128Mb this is why 32bit is needed. The thing is i only need to access the first 128Mb (in fact i really only need the first 32Mb to be exact), buy using the 24 bit adresse protocol i should be able to read that no ? Sorry again for the questions, i'm doing a lot of reading and trying to understand all this and i just need someone to tell me if i'm going in the right direction or not Best Regards, -------- Message transféré -------- Sujet : Re: [flashrom] Cannot compile flashrom for windows Date : Wed, 3 Feb 2016 02:31:54 +0100 De : Zak <zackwarrior(a)gmail.com> Pour : flashrom(a)flashrom.org Hi there, First thanks for your reply, helped me out on where to look, it was libftdi So after doing some research here and there, it looks like the libftdi was not installed right (even tho all the files were in the correct place), anyway by doing a libftdi.pc and pointing to the files i was able to compile the last version of flashrom But i get the same thing problem... Microsoft Windows [version 10.0.10240] (c) 2015 Microsoft Corporation. Tous droits réservés. C:\flashrom>flashrom flashrom v0.9.8-r1888 on Windows 6.2 (x86) flashrom is free software, get the source code at http://www.flashrom.org Please select a programmer with the --programmer parameter. Previously this was not necessary because there was a default set. Valid choices are: dummy, ft2232_spi, serprog, buspirate_spi, pony_spi, usbblaster_spi, pickit2_spi. C:\flashrom>flashrom -p ft2232_spi:type=2232H,port=A flashrom v0.9.8-r1888 on Windows 6.2 (x86) flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. No EEPROM/flash device found. Note: flashrom can never write if the flash chip isn't found automatically. C:\flashrom>flashrom -p ft2232_spi:type=2232H,port=B flashrom v0.9.8-r1888 on Windows 6.2 (x86) flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Unable to reset FTDI device (USB device unavailable). Unable to set latency timer (USB device unavailable). Unable to set bitmode to SPI (USB device unavailable). ftdi_write_data: -666, USB device unavailable Error: Programmer initialization failed. Anyway now that i got it compiled and since it looks like port A works and not port B? i guess ? Could you give me advices on how to make flashrom work with my flash chip MACRONIX_MX25L25635F? I need to modify and add the informations to flashchips.c? What about the 24 and 32bits difference? Thanks again for your help Best Regards 2016-02-02 21:01 GMT+01:00 Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at <mailto:stefan.tauner@alumni.tuwien.ac.at>>: On Tue, 2 Feb 2016 19:43:26 +0100 Bio <zackwarrior(a)gmail.com <mailto:zackwarrior@gmail.com>> wrote: > Hello, > > I'm having trouble with flashrom, i have a working ft2232 board and i > correctly connected a spi flash on it on port A > I also correctly installed the libusb drivers for the board > So i found a compiled version of flashrom for windows v0.9.6.1-r1705 > I run it with this command > flashrom -p ft2232_spi:type=2232H,port=A > And i get this: > flashrom v0.9.6.1-r1704 on Windows 6.1 (x86) > flashrom is free software, get the source code at http://www.flashrom.org > > Calibrating delay loop... OK. > No EEPROM/flash device found. > Note: flashrom can never write if the flash chip isn't found automatically. That does not tell much... the suspicion you wrote further below is correct. > I then decided to try port B, so i wired the flash chip on port B and > used this command > flashrom -p ft2232_spi:type=2232H,port=B > And i get this: > flashrom v0.9.6.1-r1704 on Windows 6.1 (x86) > flashrom is free software, get the source code at http://www.flashrom.org > > Calibrating delay loop... OK. > Unable to reset FTDI device (USB device unavailable). > Unable to set latency timer (USB device unavailable). > Unable to set bitmode to SPI (USB device unavailable). > ftdi_write_data: -666, USB device unavailable > Error: Programmer initialization failed. That looks a bit fishy but might have been fixed in the meantime. I would like to see the output for the same command line with a current version... > The chip i'm trying to work with is a MACRONIX_MX25L25635F, specified in > the flashchips.h line 478 of the source code v0.9.8 > #define MACRONIX_MX25L25635F 0x2019 /* Same as MX25L25639F, but > the latter seems to not support REMS */ > > So i decided to cross compile the new version 0.9.8 for windows thinking > that maybe the v0.9.6.1 doesn't recognise my chip ? Yes, indeed. And the current one won't help you either. The problem is that this chip requires 32 bit addresses instead of the 24 bit address used up to now in SPI flash chips. flashrom does not support this yet and so supporting your chip is not feasibly right now. There exist some patches though that would make it work. > Anyway i installed mingw and used msys64 to get all the packages and > update everything correctly, i also put the libusb and libftdi in the > bin, lib and include directory, i think everything is installed > correctly but... > When i try to compileflashrom with make i get this error > $ make > Files don't seem to be under version control. Replacing all version > templates with 0.9.8-r1888. > Package libftdi was not found in the pkg-config search path. > Perhaps you should add the directory containing `libftdi.pc' > to the PKG_CONFIG_PATH environment variable > No package 'libftdi' found > Checking for a C compiler... found. > Target arch is x86 > Target OS is MinGW > Checking for libusb-0.1/libusb-compat headers... found. > Checking if libusb-0.1 is usable... yes. > Checking for FTDI support... found. > Checking for FT232H support in libftdi... not found. > Checking for utsname support... not found. > make[1]: Entering directory `/c/flashrom/util/ich_descriptors_tool' > make[1]: Nothing to be done for `all'. > make[1]: Leaving directory `/c/flashrom/util/ich_descriptors_tool' I don't see an error. The pkgconfig message is not an error.. > And if i try with make CC=i686-w64-mingw32-gcc i get this error > $ make CC=i686-w64-mingw32-gcc > Files don't seem to be under version control. Replacing all version > templates with 0.9.8-r1888. > Package libftdi was not found in the pkg-config search path. > Perhaps you should add the directory containing `libftdi.pc' > to the PKG_CONFIG_PATH environment variable > No package 'libftdi' found > Checking for a C compiler... found. > Target arch is x86 > Target OS is MinGW > Checking for libusb-0.1/libusb-compat headers... In file included from > c:/MinGW/i686-w64-mingw32/include/stddef.h:7:0, > from > c:/MinGW/lib/gcc/i686-w64-mingw32/5.2.0/include/stddef.h:1, > from c:/MinGW/include/stdlib.h:22, > from c:/MinGW/include/lusb0_usb.h:4, > from .test.c:3: > c:/MinGW/i686-w64-mingw32/include/crtdefs.h:123:19: error: expected '=', > ',', ';', 'asm' or '__attribute__' before 'typedef' > __MINGW_EXTENSION typedef __int64 __time64_t; > ^ > c:/MinGW/i686-w64-mingw32/include/crtdefs.h:138:9: error: unknown type > name '__time64_t' > typedef __time64_t time_t; > ^ > not found. > > Please install libusb-0.1 headers or libusb-compat headers. > See README for more information. > > make: *** [hwlibs] Error 1 > > Could you help me out to compile le latest version of flashrom please ? Sounds like a bug in mingw or libusb to me... cross-compiling with mingw under Linux for Windows should work fine since a long time ago. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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W836xx: 5015AH2 (LENOVO ThinkPad L520): flashrom -V
by Loic 08 Feb '16

08 Feb '16

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hi, I just tested the following material who not yet supported: flashrom -V -p internal flashrom v0.9.7-r1852 on Linux 4.2.0-16-generic (x86_64) flashrom is free software, get the source code at http://www.flashrom.org flashrom was built with libpci 3.2.1, GCC 4.9.1, little endian Command line (3 args): flashrom -V -p internal Calibrating delay loop... OS timer resolution is 1 usecs, 1596M loops per second, 10 myus = 10 us, 100 myus = 100 us, 1000 myus = 1000 us, 10000 myus = 10010 us, 4 myus = 4 us, OK. Initializing internal programmer No coreboot table found. Using Internal DMI decoder. DMI string chassis-type: "Notebook" Laptop detected via DMI. DMI string system-manufacturer: "LENOVO" DMI string system-product-name: "5015AH2" DMI string system-version: "ThinkPad L520" DMI string baseboard-manufacturer: "LENOVO" DMI string baseboard-product-name: "5015AH2" DMI string baseboard-version: "Not Available" W836xx enter config mode worked or we were already in config mode. W836xx leave config mode had no effect. Active config mode, unknown reg 0x20 ID: 85. ... Found ITE EC, ID 0x8518, Rev 0x02 on port 0x2e. Aborting. Error: Programmer initialization failed. I am at your disposal for further testing if-necessary. Thanks - -- Best regards, Loic -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQYcBAEBAgAGBQJWuNplAAoJEOU2PAjT6toDhScv/0HC174AdSVYJr0VMF30sIW7 k67mEXjlmWFml2lsaWgId7hFV/eDtcMCJBvKKvp3yrdDKP3xftvkw1OBKlvNiIC0 NmXB3+oK4Wv1hSmqLa2+C+O0u87qcVkrMyJowootVtrX7EDSBNyRAkDNLBT+0T7A WAvzOBCXHy1b68x2jTse0HlkoKXqfmjzEmu80MM75oGFYaar2OVlrMuAQ9ExOQsJ k9hw7f0VRjPTrqFIF6T9CriimFporX2xguVR2Ah2gNQ2zgx74YA3++BhnWhVMvmx fCnsw1WV6JqfMm0M88/xM3dFlWh3RilxQImDhdxLlD8savqq67Qe8uV7pxyZ9KpU 0xdIVkRHpVell5BZdFXoDWKIJcYob4zNCdZDSwZfvTZRSf2E80Gp3dYix9puM+w7 7DJqTfAGicAOZ33oo1LIITcns3jcD7snBgfpRSPtt8v3SecU3/ex7359LgSNnWn+ D2xE/7osKtTt0eILbKpGnFlpS81LYTAGwyuYsp9BIzvhdiqVUtDgYib7JJLaD4Z3 tp4lEbAbVVAwGrjUo+HkWBh2qhApAT6sbyJlGQPXHDG1LAvZOblDwyIRDYRLzXPS VJ5fxI2xtVPt0/AopeFTLArTaFR0lGrQm1WzOntS0wiH9VOb1Jvs0UxLkcroV163 qTHoJnWQUQef1Z6GCAKUQHFhkcPQAnNF63DowJiCFUK3WdcNGYqjtzzmjot0T90Z H2LTRJvThJj0+1e/oxMvVHdXEpGlQpkqLmWf74n+mdZcyCJ5MwrZkmLjCOXwtLqU AvCS7KfzCBk+0gs9dsxJ7mkww9cOQqo35bM2c+J3tW7Y6b+6sha2lWjWl4ubNkAx 8ItxNifQU6EjfI0R1L1/6K0f6PCdu/FtagM9p20np9L8Qyl1io8yHahKLkigtnVp T9Qq8BjuC73pVQ/M2VhVBNkqI9Q3ZtcZLs3P/i9Sch5K6ayL/DGShQQNVZxgEsug h2IPTLzLQ34OWWhGNdiwaUVtwtJk4t9nCuEjvZcfXQHsCJH2W+j6/qJYYYIgwbx9 UYkdg7Tb3l8SM7xqbXWmfUAWnuojMa46BUKsCbqaxOekMZL4n64fDL0CGND/UrQ3 lktXc8Su2uJ/j77+CEf3vfljamqCkOHJgMSw+i1fqQy+MHm2LIZ+4qh2Ize+gVNZ XvI0Z1LXzk61MRTQ7yA7srYOLHCSVzYjuHrDmXzmFI5SFaIeCrktSX3BGw1HJBV7 u9gH59dYUEaZBVx41gJ0+ZhTQm/ivFeA3ITnaVmiPOJ0uxzVWi8Qkw22ih7f21Bm ZxlFPshqOG/4kozm01azqXD0oWx6mqufc/lasvOZFbKt1bnpzKmKnH8VOkiWfsw/ EgZDet5+9Qr1ay/k+5XlonsmI5qMuFsIAceBJsI0MY7RNRYXlK5OG3zrOe/75gpG 50d97Luu0vLQx0sUxGhpvAbZe5/fAiiJEyUp6oS4fpiHXaGaqAxlJvAyuMnf7p2t dtquKOBai5iz20+6m/BnX/QdegSQmwCc4hw+KtEKuPR3J2NAunVo3B/ZCnR+S1Yc CP4E0Yb8HbzBwq5/9u6SAS2h/iTlqLrMlqz9cL/laHP4nkqHb+q/byPcnP3HgNIY OvcTgZU83ufORY6hc2Mayt2KGbEkEHIvKN8o8ADMX65VptuY53jiDu/Uiz1QsCYW mgLBKXl/GZiLrPX8fF/66v83yZQbccF51qn47TWnXbm4c0fGK62c2FOVelc+xiBU ZZRJ3BzVHUKOFcyBgZetn6t0mbk+mbKo4mX0ouQlNMXm+e5tl6tN7ov22kucPYa6 CjNC1TlTjbFJpqK6BibsYqZI5H46OKtTfD7Q+rVLXBroOP9zKPB0ifyAdHmtzhGj FsrKNGY2H/aAFf4CTPdtIy+GaWarEd3Ld1yuFT3AwfLBdFalfJulvqWMee6nmpDj S7foC4CIqtbBK54SIYf5T8F/B67xpoDt1XXghiQO2soG+V24Wwx/tzmGWZjuo5kP 6TQmw9lCBY2whvLaPK4YSkw4pXOhfZeoDbz1GmZorA== =9EMC -----END PGP SIGNATURE-----

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flashrom February 2016