flashrom December 2014

flashrom@flashrom.org

27 participants
72 discussions

Re: [flashrom] Flashrom with FTDI support
by Stefan Tauner 22 Dec '14

22 Dec '14

On Thu, 18 Dec 2014 15:10:13 +0000 Ohad Benjamin <ohad(a)panpwr.com> wrote: > I tried compiling my own version from source, but the output could not communicate with the FTDI port. Hello Ohad, I'd focus on that part because from that description alone I suppose another binary would have the same problems. Please describe your symptoms and post a verbose flashrom log. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

2 1

Gigabyte GA-J1900N-D3V-1.x data
by Matt Taggart 20 Dec '14

20 Dec '14

Hi coreboot and flashrom, I recently got a Gigabyte GA-J1900N-D3V-1.x board. This board is interesting to me because A) it's Bay Trail, B) it's got dual NICs and real serial ports, and C) it's inexpensive. I followed the guide at http://www.coreboot.org/Motherboard_Porting_Guide I put the logs and a README with more info at http://lackof.org/taggart/hacking/coreboot/GA-J1900N-D3V-1.x/ (and a tarball of that dir in the parent dir) The flashrom output is from SVN trunk as of today to ensure latest chip support. In particular flashrom reports untested: Found chipset "Intel Bay Trail" with PCI ID 8086:0f1c. Found Macronix flash chip "MX25U6435E/F" (8192 kB, SPI). I haven't yet attempted anything beyond that. I don't yet have an off-board way to flash the chips, I'm hoping to order something soon. If you have ideas of other things to try please let me know. Thanks, -- Matt Taggart matt(a)lackof.org

2 3

Re: [flashrom] Unable to update BIOS for my MainBoard MS7816 =Z87-G43
by Stefan Tauner 20 Dec '14

20 Dec '14

On Mon, 17 Nov 2014 09:33:17 +0100 (CET) nabil.massaoudi(a)free.fr wrote: > another point : in Flashrom web; page Supported Hardware, noted MS7816(H87-G43), MS7816 is ref for Z87-G43. The MSI reference number is not unique but refer to a family of boards (presumably sharing the same firmware). -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

1 0

Success report
by Måns Thörnqvist 20 Dec '14

20 Dec '14

Hi! Ive successfully read and written my Gigabyte GA-P55-USB3 motherboard bios (update från F8 to F10g). This should probably be added to the list of supported hardware. Thanks for a great app! /Måns

2 3

Failed BIOS dump report
by Peter Eckersley 20 Dec '14

20 Dec '14

This is what I get with the latest flashrom from svn, running on a Thinkpad X1 Carbon (2014/Haswell edition): pde@host:~/src/flashrom$ sudo flashrom -p internal -r /tmp/blah -V flashrom v0.9.7-r1852 on Linux 3.17-1-amd64 (x86_64) flashrom is free software, get the source code at http://www.flashrom.org flashrom was built with libpci 3.2.1, GCC 4.9.1, little endian Command line (5 args): flashrom -p internal -r /tmp/blah -V Calibrating delay loop... OS timer resolution is 1 usecs, 2578M loops per second, 10 myus = 10 us, 100 myus = 127 us, 1000 myus = 1020 us, 10000 myus = 10004 us, 4 myus = 15 us, OK. Initializing internal programmer No coreboot table found. Using Internal DMI decoder. No DMI table found. W836xx enter config mode worked or we were already in config mode. W836xx leave config mode had no effect. Active config mode, unknown reg 0x20 ID: 00. Please send the output of "flashrom -V -p internal" to flashrom(a)flashrom.org with W836xx: your board name: flashrom -V as the subject to help us finish support for your Super I/O. Thanks. Found chipset "Intel Lynx Point LP Premium" with PCI ID 8086:9c43. This chipset is marked as untested. If you are using an up-to-date version of flashrom *and* were (not) able to successfully update your firmware with it, then please email a report to flashrom(a)flashrom.org including a verbose (-V) log. Thank you! Enabling flash write... Root Complex Register Block address = 0xfed1c000 GCS = 0x21: BIOS Interface Lock-Down: enabled, Boot BIOS Straps: 0x0 (SPI) Top Swap: not enabled 0xfff80000/0xffb80000 FWH IDSEL: 0x0 0xfff00000/0xffb00000 FWH IDSEL: 0x0 0xffe80000/0xffa80000 FWH IDSEL: 0x1 0xffe00000/0xffa00000 FWH IDSEL: 0x1 0xffd80000/0xff980000 FWH IDSEL: 0x2 0xffd00000/0xff900000 FWH IDSEL: 0x2 0xffc80000/0xff880000 FWH IDSEL: 0x3 0xffc00000/0xff800000 FWH IDSEL: 0x3 0xff700000/0xff300000 FWH IDSEL: 0x4 0xff600000/0xff200000 FWH IDSEL: 0x5 0xff500000/0xff100000 FWH IDSEL: 0x6 0xff400000/0xff000000 FWH IDSEL: 0x7 0xfff80000/0xffb80000 FWH decode enabled 0xfff00000/0xffb00000 FWH decode enabled 0xffe80000/0xffa80000 FWH decode enabled 0xffe00000/0xffa00000 FWH decode enabled 0xffd80000/0xff980000 FWH decode enabled 0xffd00000/0xff900000 FWH decode enabled 0xffc80000/0xff880000 FWH decode enabled 0xffc00000/0xff800000 FWH decode enabled 0xff700000/0xff300000 FWH decode enabled 0xff600000/0xff200000 FWH decode enabled 0xff500000/0xff100000 FWH decode enabled 0xff400000/0xff000000 FWH decode enabled Maximum FWH chip size: 0x100000 bytes SPI Read Configuration: prefetching enabled, caching enabled, BIOS_CNTL = 0x09: BIOS Lock Enable: disabled, BIOS Write Enable: enabled SPIBAR = 0x00007f3972d92000 + 0x3800 0x04: 0xe008 (HSFS) HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=1 Warning: SPI Configuration Lockdown activated. Reading OPCODES... done 0x06: 0x0300 (HSFC) HSFC: FGO=0, FCYCLE=0, FDBC=3, SME=0 0x50: 0x00004a4b (FRAP) BMWAG 0x00, BMRAG 0x00, BRWA 0x4a, BRRA 0x4b 0x54: 0x00000000 FREG0: Warning: Flash Descriptor region (0x00000000-0x00000fff) is read-only. 0x58: 0x07ff0180 FREG1: BIOS region (0x00180000-0x007fffff) is read-write. 0x5C: 0x017f0003 FREG2: Warning: Management Engine region (0x00003000-0x0017ffff) is locked. 0x60: 0x00020001 FREG3: Gigabit Ethernet region (0x00001000-0x00002fff) is read-write. Not all flash regions are freely accessible by flashrom. This is most likely due to an active ME. Please see http://flashrom.org/ME for details. 0x78: 0x87ff0740 PR1: Warning: 0x00740000-0x007fffff is read-only. 0x7C: 0x86df06b1 PR2: Warning: 0x006b1000-0x006dffff is read-only. 0x80: 0x86b006b0 PR3: Warning: 0x006b0000-0x006b0fff is read-only. 0x84: 0x86af0400 PR4: Warning: 0x00400000-0x006affff is read-only. Writes have been disabled for safety reasons. You can enforce write support with the ich_spi_force programmer option, but you will most likely harm your hardware! If you force flashrom you will get no support if something breaks. On a few mainboards it is possible to enable write access by setting a jumper (see its documentation or the board itself). 0x90: 0xc4 (SSFS) SSFS: SCIP=0, FDONE=1, FCERR=0, AEL=0 0x91: 0xf90000 (SSFC) SSFC: SCGO=0, ACS=0, SPOP=0, COP=0, DBC=0, SME=0, SCF=1 0x94: 0x0606 (PREOP) 0x96: 0xfe40 (OPTYPE) 0x98: 0x0135059f (OPMENU) 0x9C: 0x20d80203 (OPMENU+4) 0xA0: 0x00000000 (BBAR) 0xC4: 0x80802025 (LVSCC) LVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=1 0xC8: 0x00002025 (UVSCC) UVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20 0xD0: 0x50444653 (FPB) OK. The following protocols are supported: FWH, SPI. Probing for AMIC A25L05PT, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L05PU, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L10PT, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L10PU, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L20PT, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L20PU, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L40PT, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L40PU, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L80P, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L16PT, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L16PU, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L512, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L010, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L020, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L040, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L080, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L016, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25L032, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25LQ16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25LQ032/A25LQ32A, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for AMIC A25LQ64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25DF021, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25DF041A, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25DF081, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25DF161, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25DF321, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25DF321A, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25DF641(A), 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25DL081, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25DL161, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25DQ161, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25F512, 64 kB: Invalid OPCODE 0x15, will not execute. Probing for Atmel AT25F512A, 64 kB: Invalid OPCODE 0x15, will not execute. Probing for Atmel AT25F512B, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25F1024(A), 128 kB: Invalid OPCODE 0x15, will not execute. Probing for Atmel AT25F2048, 256 kB: Invalid OPCODE 0x15, will not execute. Probing for Atmel AT25F4096, 512 kB: Invalid OPCODE 0x15, will not execute. Probing for Atmel AT25FS010, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT25FS040, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT26DF041, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT26DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT26DF161, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT26DF161A, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT26F004, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT45CS1282, 16896 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT45DB011D, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT45DB021D, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT45DB041D, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT45DB081D, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT45DB161D, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT45DB321C, 4224 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT45DB321D, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT45DB321E, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel AT45DB642D, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for ESMT F25L008A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for ESMT F25L32PA, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B05, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B05T, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B10T, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B20T, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B40T, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B80T, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B16T, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B32T, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25B64T, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25F05, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25F10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25F20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25F40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25F80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25F16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25F32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25F64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25Q40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25Q80(A), 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25Q32(A/B), 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25QH16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25QH32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25QH64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25QH128, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25S10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25S20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25S40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25S80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25S16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25S32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon EN25S64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for GigaDevice GD25LQ32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for GigaDevice GD25Q512, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for GigaDevice GD25Q10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for GigaDevice GD25Q20(B), 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for GigaDevice GD25Q40(B), 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for GigaDevice GD25Q80(B), 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for GigaDevice GD25Q16(B), 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for GigaDevice GD25Q32(B), 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for GigaDevice GD25Q64(B), 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for GigaDevice GD25Q128B, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for GigaDevice GD25T80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Intel 25F160S33B8, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Intel 25F160S33T8, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Intel 25F320S33B8, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Intel 25F320S33T8, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Intel 25F640S33B8, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Intel 25F640S33T8, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX23L1654, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX23L3254, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX23L6454, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX23L12854, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L512(E)/MX25V512(C), 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L1005(C)/MX25L1006E, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L2005(C), 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L4005(A/C), 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L8005/MX25V8005, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L1605, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L1605A/MX25L1606E, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L1605D/MX25L1608D/MX25L1673E, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L1635D, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L1635E, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L3205(A), 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L3205D/MX25L3208D, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L3206E, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L3273E, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L3235D, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L6405(D), 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L6406E/MX25L6436E, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L6445E/MX25L6473E, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25L12805(D), 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25U1635E, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25U3235E/F, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25U6435E/F, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix MX25U12835F, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25P05-A, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25P05, 64 kB: Ignoring RES in favour of RDID. Probing for Micron/Numonyx/ST M25P10-A, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25P10, 128 kB: Ignoring RES in favour of RDID. Probing for Micron/Numonyx/ST M25P20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25P20-old, 256 kB: Ignoring RES in favour of RDID. Probing for Micron/Numonyx/ST M25P40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25P40-old, 512 kB: Ignoring RES in favour of RDID. Probing for Micron/Numonyx/ST M25P80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25P16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25P32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25P64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25P128, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25PE10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25PE20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25PE40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25PE80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25PE16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25PX80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25PX16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25PX32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M25PX64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M45PE10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M45PE20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M45PE40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M45PE80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST M45PE16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST N25Q016, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST N25Q032..1E, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST N25Q032..3E, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST N25Q064..1E, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST N25Q064..3E, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST N25Q128..1E, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Micron/Numonyx/ST N25Q128..3E, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Nantronics N25S10, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Nantronics N25S20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Nantronics N25S40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Nantronics N25S80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Nantronics N25S16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for PMC Pm25LD256C, 32 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for PMC Pm25LD512(C), 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for PMC Pm25LD010(C), 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for PMC Pm25LD020(C), 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for PMC Pm25LD040(C), 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for PMC Pm25LV512(A), 64 kB: Invalid OPCODE 0xab, will not execute. Probing for PMC Pm25LV010, 128 kB: Invalid OPCODE 0xab, will not execute. Probing for PMC Pm25LV010A, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for PMC Pm25LV020, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for PMC Pm25LV040, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for PMC Pm25LV080B, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for PMC Pm25LV016B, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Sanyo LE25FW106, 128 kB: Invalid OPCODE 0xab, will not execute. Probing for Sanyo LE25FW406A, 512 kB: Invalid OPCODE 0xab, will not execute. Probing for Sanyo LE25FU406B, 512 kB: Invalid OPCODE 0xab, will not execute. Probing for Sanyo LE25FW203A, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Sanyo LE25FW403A, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Sanyo LE25FW418A, 512 kB: Invalid OPCODE 0xab, will not execute. Probing for Sanyo LE25FW806, 1024 kB: Invalid OPCODE 0xab, will not execute. Probing for Sanyo LE25FW808, 1024 kB: Invalid OPCODE 0xab, will not execute. Probing for Spansion S25FL004A, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Spansion S25FL008A, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Spansion S25FL016A, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Spansion S25FL032A/P, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Spansion S25FL064A/P, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Spansion S25FL204K, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Spansion S25FL208K, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Spansion S25FL116K/S25FL216K, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Spansion S25FL132K, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Spansion S25FL164K, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Spansion S25FL128P......0, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Spansion S25FL128P......1, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Spansion S25FL128S......0, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Spansion S25FL128S......1, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Spansion S25FL129P......0, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Spansion S25FL129P......1, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for SST SST25LF020A, 256 kB: Invalid OPCODE 0x90, will not execute. Probing for SST SST25LF040A, 512 kB: Invalid OPCODE 0xab, will not execute. Probing for SST SST25LF080(A), 1024 kB: Invalid OPCODE 0xab, will not execute. Probing for SST SST25VF512(A), 64 kB: Invalid OPCODE 0x90, will not execute. Probing for SST SST25VF010(A), 128 kB: Invalid OPCODE 0x90, will not execute. Probing for SST SST25VF020, 256 kB: Invalid OPCODE 0x90, will not execute. Probing for SST SST25VF020B, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for SST SST25VF040, 512 kB: Invalid OPCODE 0x90, will not execute. Probing for SST SST25VF040B, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for SST SST25VF040B.REMS, 512 kB: Invalid OPCODE 0x90, will not execute. Probing for SST SST25VF080B, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for SST SST25VF016B, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for SST SST25VF032B, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for SST SST25VF064C, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for SST SST25WF512, 64 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for SST SST25WF010, 128 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for SST SST25WF020, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for SST SST25WF040, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for SST SST25WF080, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25Q40.V, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25Q80.V, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25Q16.V, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25Q32.V, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25Q64.V, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Found Winbond flash chip "W25Q64.V" (8192 kB, SPI) mapped at physical address 0x00000000ff800000. Chip status register is 0x00. Probing for Winbond W25Q128.V, 16384 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25Q20.W, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25Q40.W, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25Q80.W, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25X20, 256 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25X40, 512 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25X80, 1024 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25X16, 2048 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25X32, 4096 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond W25X64, 8192 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Unknown SFDP-capable chip, 0 kB: Invalid OPCODE 0x5a, will not execute. Receiving SFDP signature failed. Probing for AMIC unknown AMIC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Atmel unknown Atmel SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Eon unknown Eon SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Macronix unknown Macronix SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for PMC unknown PMC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for SST unknown SST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for ST unknown ST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Sanyo unknown Sanyo SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Winbond unknown Winbond (ex Nexcom) SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Generic unknown SPI chip (RDID), 0 kB: probe_spi_rdid_generic: id1 0xef, id2 0x4017 Probing for Generic unknown SPI chip (REMS), 0 kB: Invalid OPCODE 0x90, will not execute. Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0x4d, id2 0xfc, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT49LH00B4, 512 kB: probe_82802ab: id1 0x00, id2 0x6a, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT49LH004, 512 kB: probe_82802ab: id1 0x00, id2 0x6a, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0x00, id2 0x6a, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0x4d, id2 0xfc, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0x00, id2 0x6a, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0x4d, id2 0xfc, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0x44, id2 0x00, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0x00, id2 0x6a, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0x00, id2 0x6a, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 kB: probe_82802ab: id1 0xff, id2 0x99, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0x00, id2 0x6a, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0x00, id2 0x6a, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0x4d, id2 0xfc, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 kB: probe_82802ab: id1 0xff, id2 0x99, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0x00, id2 0x6a, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0x00, id2 0x6a, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0x00, id2 0x6a, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0x00, id2 0x6a, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0x4d, id2 0xfc, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0x00, id2 0x6a, id1 parity violation, id1 is normal flash content, id2 is normal flash content Found Winbond flash chip "W25Q64.V" (8192 kB, SPI). This chip may contain one-time programmable memory. flashrom cannot read and may never be able to write it, hence it may not be able to completely clone the contents of this chip (see man page for details). Reading flash... Transaction error! SSFS: SCIP=0, FDONE=1, FCERR=1, AEL=0 SSFC: SCGO=0, ACS=0, SPOP=0, COP=4, DBC=63, SME=0, SCF=1 Running OPCODE 0x03 failed at address 0x003000 (payload length was 64). Read operation failed! FAILED. Restoring MMIO space at 0x7f3972d958a0 Restoring PCI config space for 00:1f:0 reg 0xdc -- Peter Eckersley pde(a)eff.org Technology Projects Director Tel +1 415 436 9333 x131 Electronic Frontier Foundation Fax +1 415 436 9993

2 1

[commit] r1860 - trunk
by repository service 20 Dec '14

20 Dec '14

Author: stefanct Date: Sat Dec 20 21:25:19 2014 New Revision: 1860 URL: http://flashrom.org/trac/flashrom/changeset/1860 Log: Add support for the MSTAR I2C ISP protocol. Basically, among other chips, MSTAR manufactures SoCs that equip TV sets and computer screens, and it seems that all of their products use the same in-system programming protocol. Basically, they use the DDC channel of VGA or DVI connectors, which is actually an I2C bus, to encapsulate SPI frames (the flash chip is connected to the SoC through an SPI bus). I wrote this patch since the screen I bought had a software bug, and the manufacturer only released a new firmware binary, but no tool or instructions on flashing it. More details can be found here: http://boeglin.org/blog/index.php?entry=Flashing-a-BenQ-Z-series-for-free(d… I only read code from Linux kernel archives published by Acer to figure out the protocol (for a touchscreen controller and an NFC chip, both by MSTAR, that share the same ISP protocol), so I don't think there are any legal problems with it. Compilation is currently disabled by default in the Makefile. If in doubt, additional Makefile bugs were added by Stefan. Signed-off-by: Alexandre Boeglin <alex(a)boeglin.org> Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Added: trunk/mstarddc_spi.c (contents, props changed) Modified: trunk/Makefile trunk/flashrom.8.tmpl trunk/flashrom.c trunk/programmer.h Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Sat Dec 20 17:45:31 2014 (r1859) +++ trunk/Makefile Sat Dec 20 21:25:19 2014 (r1860) @@ -300,6 +300,11 @@ else override CONFIG_LINUX_SPI = no endif +ifeq ($(CONFIG_MSTARDDC_SPI), yes) +UNSUPPORTED_FEATURES += CONFIG_MSTARDDC_SPI=yes +else +override CONFIG_MSTARDDC_SPI = no +endif endif ############################################################################### @@ -413,6 +418,9 @@ # Always enable Altera USB-Blaster dongles for now. CONFIG_USBBLASTER_SPI ?= yes +# MSTAR DDC support needs more tests/reviews/cleanups. +CONFIG_MSTARDDC_SPI ?= no + # Always enable dummy tracing for now. CONFIG_DUMMY ?= yes @@ -670,6 +678,13 @@ PROGRAMMER_OBJS += linux_spi.o endif +ifeq ($(CONFIG_MSTARDDC_SPI), yes) +# This is a totally ugly hack. +FEATURE_CFLAGS += $(shell LC_ALL=C grep -q "LINUX_I2C_SUPPORT := yes" .features && printf "%s" "-D'CONFIG_MSTARDDC_SPI=1'") +NEED_LINUX_I2C := yes +PROGRAMMER_OBJS += mstarddc_spi.o +endif + ifeq ($(NEED_SERIAL), yes) LIB_OBJS += serial.o endif @@ -927,6 +942,19 @@ endef export LINUX_SPI_TEST +define LINUX_I2C_TEST +#include <linux/i2c-dev.h> +#include <linux/i2c.h> + +int main(int argc, char **argv) +{ + (void) argc; + (void) argv; + return 0; +} +endef +export LINUX_I2C_TEST + features: compiler @echo "FEATURES := yes" > .features.tmp ifeq ($(NEED_FTDI), yes) @@ -948,6 +976,13 @@ ( echo "yes."; echo "LINUX_SPI_SUPPORT := yes" >> .features.tmp ) || \ ( echo "no."; echo "LINUX_SPI_SUPPORT := no" >> .features.tmp ) endif +ifeq ($(NEED_LINUX_I2C), yes) + @printf "Checking if Linux I2C headers are present... " + @echo "$$LINUX_I2C_TEST" > .featuretest.c + @$(CC) $(CPPFLAGS) $(CFLAGS) $(LDFLAGS) .featuretest.c -o .featuretest$(EXEC_SUFFIX) >/dev/null 2>&1 && \ + ( echo "yes."; echo "LINUX_I2C_SUPPORT := yes" >> .features.tmp ) || \ + ( echo "no."; echo "LINUX_I2C_SUPPORT := no" >> .features.tmp ) +endif @printf "Checking for utsname support... " @echo "$$UTSNAME_TEST" > .featuretest.c @$(CC) $(CPPFLAGS) $(CFLAGS) $(LDFLAGS) .featuretest.c -o .featuretest$(EXEC_SUFFIX) >/dev/null 2>&1 && \ Modified: trunk/flashrom.8.tmpl ============================================================================== --- trunk/flashrom.8.tmpl Sat Dec 20 17:45:31 2014 (r1859) +++ trunk/flashrom.8.tmpl Sat Dec 20 21:25:19 2014 (r1860) @@ -227,6 +227,8 @@ .sp .BR "* nicintel_eeprom" " (for SPI EEPROMs on Intel Gigabit network cards)" .sp +.BR "* mstarddc_spi" " (for SPI flash ROMs accessible through DDC in MSTAR-equipped displays)" +.sp Some programmers have optional or mandatory parameters which are described in detail in the .B PROGRAMMER-SPECIFIC INFORMATION @@ -889,6 +891,51 @@ .B " flashrom \-p linux_spi:dev=/dev/spidevX.Y,spispeed=8000" .sp Please note that the linux_spi driver only works on Linux. +.SS +.BR "mstarddc_spi " programmer +The Display Data Channel (DDC) is an I2C bus present on VGA and DVI connectors, that allows exchanging +informations between a computer and attached displays. Its most common uses are getting display capabilities +through EDID (at I2C address 0x50) and sending commands to the display using the DDC/CI protocol (at address +0x37). On displays driven by MSTAR SoCs, it is also possible to access the SoC firmware flash (connected to +the Soc through another SPI bus) using an In-System Programming (ISP) port, usually at address 0x49. +This flashrom module allows the latter via Linux's I2C driver. +.sp +.B IMPORTANT: +Before using this programmer, the display +.B MUST +be in standby mode, and only connected to the computer that will run flashrom using a VGA cable, to an +inactive VGA output. It absolutely +.B MUST NOT +be used as a display during the procedure! +.sp +You have to specify the DDC/I2C controller and I2C address to use with the +.sp +.B " flashrom \-p mstarddc_spi:dev=/dev/i2c-X:YY" +.sp +syntax where +.B /dev/i2c-X +is the Linux device node for your I2C controller connected to the display's DDC channel, and +.B YY +is the (hexadecimal) address of the MSTAR ISP port (address 0x49 is usually used). +Example that uses I2C controller /dev/i2c-1 and address 0x49: +.sp +.B " flashrom \-p mstarddc_spi:dev=/dev/i2c-1:49 +.sp +It is also possible to inhibit the reset command that is normally sent to the display once the flashrom +operation is completed using the optional +.B noreset +parameter. A value of 1 prevents flashrom from sending the reset command. +Example that does not reset the display at the end of the operation: +.sp +.B " flashrom \-p mstarddc_spi:dev=/dev/i2c-1:49,noreset=1 +.sp +Please note that sending the reset command is also inhibited in the event an error occured during the operation. +To send the reset command afterwards, you can simply run flashrom once more, in chip probe mode (not specifying +an operation), without the +.B noreset +parameter, once the flash read/write operation you intended to perform has completed successfully. +.sp +Please also note that the mstarddc_spi driver only works on Linux. .SH EXAMPLES To back up and update your BIOS, run .sp Modified: trunk/flashrom.c ============================================================================== --- trunk/flashrom.c Sat Dec 20 17:45:31 2014 (r1859) +++ trunk/flashrom.c Sat Dec 20 21:25:19 2014 (r1860) @@ -354,6 +354,18 @@ }, #endif +#if CONFIG_MSTARDDC_SPI == 1 + { + .name = "mstarddc_spi", + .type = OTHER, + .devs.note = "MSTAR DDC devices addressable via /dev/i2c-* on Linux.\n", + .init = mstarddc_spi_init, + .map_flash_region = fallback_map, + .unmap_flash_region = fallback_unmap, + .delay = internal_delay, + }, +#endif + {0}, /* This entry corresponds to PROGRAMMER_INVALID. */ }; Added: trunk/mstarddc_spi.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/mstarddc_spi.c Sat Dec 20 21:25:19 2014 (r1860) @@ -0,0 +1,234 @@ +/* + * This file is part of the flashrom project. + * + * Copyright (C) 2014 Alexandre Boeglin <alex(a)boeglin.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#if CONFIG_MSTARDDC_SPI == 1 + +#include <stdio.h> +#include <string.h> +#include <stdlib.h> +#include <ctype.h> +#include <sys/types.h> +#include <sys/stat.h> +#include <fcntl.h> +#include <unistd.h> +#include <errno.h> +#include <sys/ioctl.h> +#include <linux/i2c-dev.h> +#include <linux/i2c.h> +#include "flash.h" +#include "programmer.h" +#include "spi.h" + +static const struct spi_master spi_master_mstarddc; + +static int mstarddc_fd; +static int mstarddc_addr; +static int mstarddc_doreset = 1; + +// MSTAR DDC Commands +#define MSTARDDC_SPI_WRITE 0x10 +#define MSTARDDC_SPI_READ 0x11 +#define MSTARDDC_SPI_END 0x12 +#define MSTARDDC_SPI_RESET 0x24 + +/* Returns 0 upon success, a negative number upon errors. */ +static int mstarddc_spi_shutdown(void *data) +{ + // Reset, disables ISP mode + if (mstarddc_doreset == 1) { + uint8_t cmd = MSTARDDC_SPI_RESET; + if (write(mstarddc_fd, &cmd, 1) < 0) { + msg_perr("Error sending reset command: errno %d.\n", + errno); + return -1; + } + } else { + msg_pinfo("Info: Reset command was not sent. " + "Either the noreset=1 option was used, " + "or an error occured.\n"); + } + + if (close(mstarddc_fd) < 0) { + msg_perr("Error closing device: errno %d.\n", errno); + return -1; + } + return 0; +} + +/* Returns 0 upon success, a negative number upon errors. */ +int mstarddc_spi_init(void) +{ + char *i2c_device; + char *i2c_address; + char *noreset; + + // Get device, address from command-line + i2c_device = extract_programmer_param("dev"); + if (i2c_device && strlen(i2c_device)) { + if ((i2c_address = strchr(i2c_device, ':'))) { + *i2c_address = '\0'; + i2c_address++; + } + if (!i2c_address || !strlen(i2c_address)) { + msg_perr("Error: no address specified.\n" + "Use flashrom -p mstarddc_spi:dev=/dev/device:address.\n"); + return -1; + } + mstarddc_addr = strtol(i2c_address, NULL, 16); + } else { + msg_perr("Error: no device specified.\n" + "Use flashrom -p mstarddc_spi:dev=/dev/device:address.\n"); + return -1; + } + msg_pinfo("Info: Will try to use device %s and address 0x%02x.\n", + i2c_device, mstarddc_addr); + + // Get noreset=1 option from command-line + if ((noreset = extract_programmer_param("noreset")) + && noreset[0] == '1') + mstarddc_doreset = 0; + msg_pinfo("Info: WILL %sreset the device at the end.\n", + mstarddc_doreset ? "" : "NOT "); + // Open device + if ((mstarddc_fd = open(i2c_device, O_RDWR)) < 0) { + switch (errno) { + case EACCES: + msg_perr("Error opening %s: Permission denied.\n" + "Please use sudo or run as root.\n", + i2c_device); + break; + case ENOENT: + msg_perr("Error opening %s: No such file.\n" + "Please check you specified the correct device.\n", + i2c_device); + break; + default: + msg_perr("Error opening %s: errno %d.\n", + i2c_device, errno); + } + return -1; + } + // Set slave address + if (ioctl(mstarddc_fd, I2C_SLAVE, mstarddc_addr) < 0) { + msg_perr("Error setting slave address 0x%02x: errno %d.\n", + mstarddc_addr, errno); + return -1; + } + // Enable ISP mode + uint8_t cmd[5] = { 'M', 'S', 'T', 'A', 'R' }; + if (write(mstarddc_fd, cmd, 5) < 0) { + int enable_err = errno; + uint8_t end_cmd = MSTARDDC_SPI_END; + + // Assume device is already in ISP mode, try to send END command + if (write(mstarddc_fd, &end_cmd, 1) < 0) { + msg_perr("Error enabling ISP mode: errno %d & %d.\n" + "Please check that device (%s) and address (0x%02x) are correct.\n", + enable_err, errno, i2c_device, mstarddc_addr); + return -1; + } + } + // Register shutdown function + register_shutdown(mstarddc_spi_shutdown, NULL); + + // Register programmer + register_spi_master(&spi_master_mstarddc); + return 0; +} + +/* Returns 0 upon success, a negative number upon errors. */ +static int mstarddc_spi_send_command(struct flashctx *flash, + unsigned int writecnt, + unsigned int readcnt, + const unsigned char *writearr, + unsigned char *readarr) +{ + int ret = 0; + uint8_t *cmd; + + if ((cmd = malloc((writecnt + 1) * sizeof(uint8_t))) < 0) { + msg_perr("Error allocating memory: errno %d.\n", errno); + ret = -1; + } + + if (!ret && writecnt) { + cmd[0] = MSTARDDC_SPI_WRITE; + memcpy(cmd + 1, writearr, writecnt); + if (write(mstarddc_fd, cmd, writecnt + 1) < 0) { + msg_perr("Error sending write command: errno %d.\n", + errno); + ret = -1; + } + } + + if (!ret && readcnt) { + struct i2c_rdwr_ioctl_data i2c_data; + struct i2c_msg msg[2]; + + cmd[0] = MSTARDDC_SPI_READ; + i2c_data.nmsgs = 2; + i2c_data.msgs = msg; + i2c_data.msgs[0].addr = mstarddc_addr; + i2c_data.msgs[0].len = 1; + i2c_data.msgs[0].flags = 0; + i2c_data.msgs[0].buf = cmd; + i2c_data.msgs[1].addr = mstarddc_addr; + i2c_data.msgs[1].len = readcnt; + i2c_data.msgs[1].flags = I2C_M_RD; + i2c_data.msgs[1].buf = readarr; + + if (ioctl(mstarddc_fd, I2C_RDWR, &i2c_data) < 0) { + msg_perr("Error sending read command: errno %d.\n", + errno); + ret = -1; + } + } + + if (!ret && (writecnt || readcnt)) { + cmd[0] = MSTARDDC_SPI_END; + if (write(mstarddc_fd, cmd, 1) < 0) { + msg_perr("Error sending end command: errno %d.\n", + errno); + ret = -1; + } + } + + /* Do not reset if something went wrong, as it might prevent from + * retrying flashing. */ + if (ret != 0) + mstarddc_doreset = 0; + + if (cmd) + free(cmd); + + return ret; +} + +static const struct spi_master spi_master_mstarddc = { + .type = SPI_CONTROLLER_MSTARDDC, + .max_data_read = 256, + .max_data_write = 256, + .command = mstarddc_spi_send_command, + .multicommand = default_spi_send_multicommand, + .read = default_spi_read, + .write_256 = default_spi_write_256, + .write_aai = default_spi_write_aai, +}; + +#endif Modified: trunk/programmer.h ============================================================================== --- trunk/programmer.h Sat Dec 20 17:45:31 2014 (r1859) +++ trunk/programmer.h Sat Dec 20 21:25:19 2014 (r1860) @@ -99,6 +99,9 @@ #if CONFIG_USBBLASTER_SPI == 1 PROGRAMMER_USBBLASTER_SPI, #endif +#if CONFIG_MSTARDDC_SPI == 1 + PROGRAMMER_MSTARDDC_SPI, +#endif PROGRAMMER_INVALID /* This must always be the last entry. */ }; @@ -474,6 +477,11 @@ extern const struct dev_entry devs_usbblasterspi[]; #endif +/* mstarddc_spi.c */ +#if CONFIG_MSTARDDC_SPI == 1 +int mstarddc_spi_init(void); +#endif + /* rayer_spi.c */ #if CONFIG_RAYER_SPI == 1 int rayer_spi_init(void); @@ -555,6 +563,9 @@ #if CONFIG_USBBLASTER_SPI == 1 SPI_CONTROLLER_USBBLASTER, #endif +#if CONFIG_MSTARDDC_SPI == 1 + SPI_CONTROLLER_MSTARDDC, +#endif }; #define MAX_DATA_UNSPECIFIED 0

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Re: [flashrom] [PATCH] Fix handling of write protection at register space address +2.
by Stefan Tauner 20 Dec '14

20 Dec '14

On Sat, 20 Dec 2014 20:30:09 +0400 Roman Lebedev <lebedev.ri(a)gmail.com> wrote: Thanks for all the tests. I have committed the last version in r1859. > The only two lines that look suspicious are: > W836xx enter config mode worked or we were already in config mode. > W836xx leave config mode had no effect. > Active config mode, unknown reg 0x20 ID: 00. > Is that normal? That's because flashrom lacks support for the superio/EC on the board and that's the cryptic message it spits out to tell us that. It is of no concern in most cases (i.e. when we can access the flash chip without help from the EC). -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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[commit] r1859 - trunk
by repository service 20 Dec '14

20 Dec '14

Author: stefanct Date: Sat Dec 20 17:45:31 2014 New Revision: 1859 URL: http://flashrom.org/trac/flashrom/changeset/1859 Log: Fix handling of write protection at register space address +2. Since r1833 we added the offset of the virtual register in several functions, which produced segfaults. This patch renames a few parameters and reorganizes/fixes various parts of the changelock_regspace2_block() function - hence the rather big diff. Thanks to Roman Lebedev for reporting this issue and testing numerous revisions of this patch. Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Modified: trunk/chipdrivers.h trunk/jedec.c Modified: trunk/chipdrivers.h ============================================================================== --- trunk/chipdrivers.h Fri Dec 12 01:32:03 2014 (r1858) +++ trunk/chipdrivers.h Sat Dec 20 17:45:31 2014 (r1859) @@ -150,7 +150,6 @@ int unlock_regspace2_uniform_64k(struct flashctx *flash); int unlock_regspace2_block_eraser_0(struct flashctx *flash); int unlock_regspace2_block_eraser_1(struct flashctx *flash); -int unlock_regspace2_block(const struct flashctx *flash, chipaddr off); int printlock_regspace2_uniform_64k(struct flashctx *flash); int printlock_regspace2_block_eraser_0(struct flashctx *flash); int printlock_regspace2_block_eraser_1(struct flashctx *flash); Modified: trunk/jedec.c ============================================================================== --- trunk/jedec.c Fri Dec 12 01:32:03 2014 (r1858) +++ trunk/jedec.c Sat Dec 20 17:45:31 2014 (r1859) @@ -589,11 +589,10 @@ #define REG2_LOCKDOWN (1 << 1) #define REG2_MASK (REG2_RWLOCK | REG2_LOCKDOWN) -static int printlock_regspace2_block(const struct flashctx *flash, chipaddr offset) +static int printlock_regspace2_block(const struct flashctx *flash, chipaddr lockreg) { - chipaddr wrprotect = flash->virtual_registers + offset + 2; - uint8_t state = chip_readb(flash, wrprotect); - msg_cdbg("Lock status of block at 0x%0*" PRIxPTR " is ", PRIxPTR_WIDTH, offset); + uint8_t state = chip_readb(flash, lockreg); + msg_cdbg("Lock status of block at 0x%0*" PRIxPTR " is ", PRIxPTR_WIDTH, lockreg); switch (state & REG2_MASK) { case 0: msg_cdbg("Full Access.\n"); @@ -656,67 +655,81 @@ return regspace2_walk_unlockblocks(flash, unlockblocks, &printlock_regspace2_block); } -static int changelock_regspace2_block(const struct flashctx *flash, chipaddr offset, uint8_t new_bits) -{ - chipaddr wrprotect = flash->virtual_registers + offset + 2; - uint8_t old; - - if (new_bits & ~REG2_MASK) { - msg_cerr("Invalid locking change 0x%02x requested at 0x%0*" PRIxPTR "! " +/* Try to change the lock register at address lockreg from cur to new. + * + * - Try to unlock the lock bit if requested and it is currently set (although this is probably futile). + * - Try to change the read/write bits if requested. + * - Try to set the lockdown bit if requested. + * Return an error immediately if any of this fails. */ +static int changelock_regspace2_block(const struct flashctx *flash, chipaddr lockreg, uint8_t cur, uint8_t new) +{ + /* Only allow changes to known read/write/lockdown bits */ + if (((cur ^ new) & ~REG2_MASK) != 0) { + msg_cerr("Invalid lock change from 0x%02x to 0x%02x requested at 0x%0*" PRIxPTR "!\n" "Please report a bug at flashrom(a)flashrom.org\n", - new_bits, PRIxPTR_WIDTH, offset); + cur, new, PRIxPTR_WIDTH, lockreg); return -1; } - old = chip_readb(flash, wrprotect); - /* Early exist if no change (of read/write/lockdown) was requested. */ - if (((old ^ new_bits) & REG2_MASK) == 0) { - msg_cdbg2("Locking status at 0x%0*" PRIxPTR " not changed\n", PRIxPTR_WIDTH, offset); + + /* Exit early if no change (of read/write/lockdown bits) was requested. */ + if (((cur ^ new) & REG2_MASK) == 0) { + msg_cdbg2("Lock bits at 0x%0*" PRIxPTR " not changed.\n", PRIxPTR_WIDTH, lockreg); return 0; } - /* Normally lockdowns can not be cleared. Try nevertheless if requested. */ - if ((old & REG2_LOCKDOWN) && !(new_bits & REG2_LOCKDOWN)) { - chip_writeb(flash, old & ~REG2_LOCKDOWN, wrprotect); - if (chip_readb(flash, wrprotect) != (old & ~REG2_LOCKDOWN)) { - msg_cerr("Lockdown can't be removed at 0x%0*" PRIxPTR "!\n", PRIxPTR_WIDTH, offset); + + /* Normally the lockdown bit can not be cleared. Try nevertheless if requested. */ + if ((cur & REG2_LOCKDOWN) && !(new & REG2_LOCKDOWN)) { + chip_writeb(flash, cur & ~REG2_LOCKDOWN, lockreg); + cur = chip_readb(flash, lockreg); + if ((cur & REG2_LOCKDOWN) == REG2_LOCKDOWN) { + msg_cwarn("Lockdown can't be removed at 0x%0*" PRIxPTR "! New value: 0x%02x.\n", + PRIxPTR_WIDTH, lockreg, cur); return -1; } } - /* Change read or write lock? */ - if ((old ^ new_bits) & REG2_RWLOCK) { + + /* Change read and/or write bit */ + if ((cur ^ new) & REG2_RWLOCK) { /* Do not lockdown yet. */ - msg_cdbg("Changing locking status at 0x%0*" PRIxPTR " to 0x%02x\n", PRIxPTR_WIDTH, offset, new_bits & REG2_RWLOCK); - chip_writeb(flash, new_bits & REG2_RWLOCK, wrprotect); - if (chip_readb(flash, wrprotect) != (new_bits & REG2_RWLOCK)) { - msg_cerr("Locking status change FAILED at 0x%0*" PRIxPTR "!\n", PRIxPTR_WIDTH, offset); + uint8_t wanted = (cur & ~REG2_RWLOCK) | (new & REG2_RWLOCK); + chip_writeb(flash, wanted, lockreg); + cur = chip_readb(flash, lockreg); + if (cur != wanted) { + msg_cerr("Changing lock bits failed at 0x%0*" PRIxPTR "! New value: 0x%02x.\n", + PRIxPTR_WIDTH, lockreg, cur); return -1; } + msg_cdbg("Changed lock bits at 0x%0*" PRIxPTR " to 0x%02x.\n", + PRIxPTR_WIDTH, lockreg, cur); } - /* Enable lockdown if requested. */ - if (!(old & REG2_LOCKDOWN) && (new_bits & REG2_LOCKDOWN)) { - msg_cdbg("Enabling lockdown at 0x%0*" PRIxPTR "\n", PRIxPTR_WIDTH, offset); - chip_writeb(flash, new_bits, wrprotect); - if (chip_readb(flash, wrprotect) != new_bits) { - msg_cerr("Enabling lockdown FAILED at 0x%0*" PRIxPTR "!\n", PRIxPTR_WIDTH, offset); + + /* Eventually, enable lockdown if requested. */ + if (!(cur & REG2_LOCKDOWN) && (new & REG2_LOCKDOWN)) { + chip_writeb(flash, new, lockreg); + cur = chip_readb(flash, lockreg); + if (cur != new) { + msg_cerr("Enabling lockdown FAILED at 0x%0*" PRIxPTR "! New value: 0x%02x.\n", + PRIxPTR_WIDTH, lockreg, cur); return -1; } + msg_cdbg("Enabled lockdown at 0x%0*" PRIxPTR ".\n", PRIxPTR_WIDTH, lockreg); } return 0; } -int unlock_regspace2_block(const struct flashctx *flash, chipaddr off) +static int unlock_regspace2_block_generic(const struct flashctx *flash, chipaddr lockreg) { - chipaddr wrprotect = flash->virtual_registers + off + 2; - uint8_t old = chip_readb(flash, wrprotect); + uint8_t old = chip_readb(flash, lockreg); /* We don't care for the lockdown bit as long as the RW locks are 0 after we're done */ - return changelock_regspace2_block(flash, off, old & ~REG2_RWLOCK); + return changelock_regspace2_block(flash, lockreg, old, old & ~REG2_RWLOCK); } static int unlock_regspace2_uniform(struct flashctx *flash, unsigned long block_size) { const unsigned int elems = flash->chip->total_size * 1024 / block_size; struct unlockblock blocks[2] = {{.size = block_size, .count = elems}}; - return regspace2_walk_unlockblocks(flash, blocks, &unlock_regspace2_block); + return regspace2_walk_unlockblocks(flash, blocks, &unlock_regspace2_block_generic); } int unlock_regspace2_uniform_64k(struct flashctx *flash) @@ -734,7 +747,7 @@ // FIXME: this depends on the eraseblocks not to be filled up completely (i.e. to be null-terminated). const struct unlockblock *unlockblocks = (const struct unlockblock *)flash->chip->block_erasers[0].eraseblocks; - return regspace2_walk_unlockblocks(flash, unlockblocks, &unlock_regspace2_block); + return regspace2_walk_unlockblocks(flash, unlockblocks, &unlock_regspace2_block_generic); } int unlock_regspace2_block_eraser_1(struct flashctx *flash) @@ -742,6 +755,6 @@ // FIXME: this depends on the eraseblocks not to be filled up completely (i.e. to be null-terminated). const struct unlockblock *unlockblocks = (const struct unlockblock *)flash->chip->block_erasers[1].eraseblocks; - return regspace2_walk_unlockblocks(flash, unlockblocks, &unlock_regspace2_block); + return regspace2_walk_unlockblocks(flash, unlockblocks, &unlock_regspace2_block_generic); }

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Re: [flashrom] [PATCH] Fix handling of write protection at register space address +2.
by Roman Lebedev 20 Dec '14

20 Dec '14

Hi. > Third time lucky. It indeed looks like to be a case here :) # flashrom --programmer internal -r 1002.bin.patch4 -V flashrom v0.9.7-r1858 on Linux 3.16.0-4-686-pae (i686) flashrom is free software, get the source code at http://www.flashrom.org flashrom was built with libpci 3.2.1, GCC 4.9.2, little endian Command line (5 args): flashrom --programmer internal -r 1002.bin.patch4 -V Calibrating delay loop... OS timer resolution is 1 usecs, 534M loops per second, 10 myus = 11 us, 100 myus = 107 us, 1000 myus = 1024 us, 10000 myus = 10026 us, 4 myus = 5 us, OK. Initializing internal programmer No coreboot table found. Using Internal DMI decoder. DMI string chassis-type: "Desktop" DMI string system-manufacturer: "ASUSTeK COMPUTER INC." DMI string system-product-name: "PCH-DR" DMI string system-version: "1.XX " DMI string baseboard-manufacturer: "ASUSTek Computer INC." DMI string baseboard-product-name: "PCH-DR" DMI string baseboard-version: "1.XX " Found Winbond Super I/O, id 0x82 W836xx enter config mode worked or we were already in config mode. W836xx leave config mode had no effect. Active config mode, unknown reg 0x20 ID: 00. Please send the output of "flashrom -V -p internal" to flashrom(a)flashrom.org with W836xx: your board name: flashrom -V as the subject to help us finish support for your Super I/O. Thanks. Found chipset "Intel 6300ESB" with PCI ID 8086:25a1. Enabling flash write... 0xfff80000/0xffb80000 FWH IDSEL: 0x0 0xfff00000/0xffb00000 FWH IDSEL: 0x0 0xffe80000/0xffa80000 FWH IDSEL: 0x1 0xffe00000/0xffa00000 FWH IDSEL: 0x1 0xffd80000/0xff980000 FWH IDSEL: 0x2 0xffd00000/0xff900000 FWH IDSEL: 0x2 0xffc80000/0xff880000 FWH IDSEL: 0x3 0xffc00000/0xff800000 FWH IDSEL: 0x3 0xff700000/0xff300000 FWH IDSEL: 0x4 0xff600000/0xff200000 FWH IDSEL: 0x5 0xff500000/0xff100000 FWH IDSEL: 0x6 0xff400000/0xff000000 FWH IDSEL: 0x7 0xfff80000/0xffb80000 FWH decode enabled 0xfff00000/0xffb00000 FWH decode enabled 0xffe80000/0xffa80000 FWH decode disabled 0xffe00000/0xffa00000 FWH decode disabled 0xffd80000/0xff980000 FWH decode disabled 0xffd00000/0xff900000 FWH decode disabled 0xffc80000/0xff880000 FWH decode disabled 0xffc00000/0xff800000 FWH decode disabled 0xff700000/0xff300000 FWH decode disabled 0xff600000/0xff200000 FWH decode disabled 0xff500000/0xff100000 FWH decode disabled 0xff400000/0xff000000 FWH decode disabled Maximum FWH chip size: 0x100000 bytes BIOS_CNTL = 0x01: BIOS Lock Enable: disabled, BIOS Write Enable: enabled OK. The following protocols are supported: FWH. Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0x08, id2 0x14, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT49LH00B4, 512 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT49LH004, 512 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Found PMC flash chip "Pm49FL004" (512 kB, LPC, FWH) mapped at physical address 0xfff80000. Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0x08, id2 0x14, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Found PMC flash chip "Pm49FL004" (512 kB, LPC, FWH). === This flash part has status UNTESTED for operations: ERASE WRITE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash chip. Please include the flashrom log file for all operations you tested (see the man page for details), and mention which mainboard or programmer you tested in the subject line. Thanks for your help! Changed lock bits at 0xb733a002 to 0xf8. Changed lock bits at 0xb734a002 to 0xf8. Changed lock bits at 0xb735a002 to 0xf8. Changed lock bits at 0xb736a002 to 0xf8. Changed lock bits at 0xb737a002 to 0xf8. Changed lock bits at 0xb738a002 to 0xf8. Changed lock bits at 0xb739a002 to 0xf8. Changed lock bits at 0xb73aa002 to 0xf8. Reading flash... done. Restoring PCI config space for 00:1f:0 reg 0x4e The only two lines that look suspicious are: W836xx enter config mode worked or we were already in config mode. W836xx leave config mode had no effect. Active config mode, unknown reg 0x20 ID: 00. Is that normal? Thanks for this patches! Roman. On Sat, Dec 20, 2014 at 7:07 PM, Stefan Tauner < stefan.tauner(a)alumni.tuwien.ac.at> wrote: > Previously we added the offset of the virtual register in several > functions, > which produced segfaults. This patch renames a few parameters and > reorganizes/fixes various parts of the changelock_regspace2_block() > function - hence the rather big diff. > > Thanks to Roman Lebedev for reporting this issue and testing numerous > revisions of this patch. > > Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> > --- > > $"!%§$&%%$"Q! > Third time lucky. > Sorry everybody for the spam. > > chipdrivers.h | 1 - > jedec.c | 93 > ++++++++++++++++++++++++++++++++++------------------------- > 2 files changed, 53 insertions(+), 41 deletions(-) > > diff --git a/chipdrivers.h b/chipdrivers.h > index 8529c74..cac94f3 100644 > --- a/chipdrivers.h > +++ b/chipdrivers.h > @@ -150,7 +150,6 @@ int unlock_regspace2_uniform_32k(struct flashctx > *flash); > int unlock_regspace2_uniform_64k(struct flashctx *flash); > int unlock_regspace2_block_eraser_0(struct flashctx *flash); > int unlock_regspace2_block_eraser_1(struct flashctx *flash); > -int unlock_regspace2_block(const struct flashctx *flash, chipaddr off); > int printlock_regspace2_uniform_64k(struct flashctx *flash); > int printlock_regspace2_block_eraser_0(struct flashctx *flash); > int printlock_regspace2_block_eraser_1(struct flashctx *flash); > diff --git a/jedec.c b/jedec.c > index 1345b89..19babf9 100644 > --- a/jedec.c > +++ b/jedec.c > @@ -589,11 +589,10 @@ static int regspace2_walk_unlockblocks(const struct > flashctx *flash, const struc > #define REG2_LOCKDOWN (1 << 1) > #define REG2_MASK (REG2_RWLOCK | REG2_LOCKDOWN) > > -static int printlock_regspace2_block(const struct flashctx *flash, > chipaddr offset) > +static int printlock_regspace2_block(const struct flashctx *flash, > chipaddr lockreg) > { > - chipaddr wrprotect = flash->virtual_registers + offset + 2; > - uint8_t state = chip_readb(flash, wrprotect); > - msg_cdbg("Lock status of block at 0x%0*" PRIxPTR " is ", > PRIxPTR_WIDTH, offset); > + uint8_t state = chip_readb(flash, lockreg); > + msg_cdbg("Lock status of block at 0x%0*" PRIxPTR " is ", > PRIxPTR_WIDTH, lockreg); > switch (state & REG2_MASK) { > case 0: > msg_cdbg("Full Access.\n"); > @@ -656,67 +655,81 @@ int printlock_regspace2_block_eraser_1(struct > flashctx *flash) > return regspace2_walk_unlockblocks(flash, unlockblocks, > &printlock_regspace2_block); > } > > -static int changelock_regspace2_block(const struct flashctx *flash, > chipaddr offset, uint8_t new_bits) > -{ > - chipaddr wrprotect = flash->virtual_registers + offset + 2; > - uint8_t old; > - > - if (new_bits & ~REG2_MASK) { > - msg_cerr("Invalid locking change 0x%02x requested at > 0x%0*" PRIxPTR "! " > +/* Try to change the lock register at address lockreg from cur to new. > + * > + * - Try to unlock the lock bit if requested and it is currently set > (although this is probably futile). > + * - Try to change the read/write bits if requested. > + * - Try to set the lockdown bit if requested. > + * Return an error immediately if any of this fails. */ > +static int changelock_regspace2_block(const struct flashctx *flash, > chipaddr lockreg, uint8_t cur, uint8_t new) > +{ > + /* Only allow changes to known read/write/lockdown bits */ > + if (((cur ^ new) & ~REG2_MASK) != 0) { > + msg_cerr("Invalid lock change from 0x%02x to 0x%02x > requested at 0x%0*" PRIxPTR "!\n" > "Please report a bug at flashrom(a)flashrom.org\n", > - new_bits, PRIxPTR_WIDTH, offset); > + cur, new, PRIxPTR_WIDTH, lockreg); > return -1; > } > - old = chip_readb(flash, wrprotect); > - /* Early exist if no change (of read/write/lockdown) was > requested. */ > - if (((old ^ new_bits) & REG2_MASK) == 0) { > - msg_cdbg2("Locking status at 0x%0*" PRIxPTR " not > changed\n", PRIxPTR_WIDTH, offset); > + > + /* Exit early if no change (of read/write/lockdown bits) was > requested. */ > + if (((cur ^ new) & REG2_MASK) == 0) { > + msg_cdbg2("Lock bits at 0x%0*" PRIxPTR " not changed.\n", > PRIxPTR_WIDTH, lockreg); > return 0; > } > - /* Normally lockdowns can not be cleared. Try nevertheless if > requested. */ > - if ((old & REG2_LOCKDOWN) && !(new_bits & REG2_LOCKDOWN)) { > - chip_writeb(flash, old & ~REG2_LOCKDOWN, wrprotect); > - if (chip_readb(flash, wrprotect) != (old & > ~REG2_LOCKDOWN)) { > - msg_cerr("Lockdown can't be removed at 0x%0*" > PRIxPTR "!\n", PRIxPTR_WIDTH, offset); > + > + /* Normally the lockdown bit can not be cleared. Try nevertheless > if requested. */ > + if ((cur & REG2_LOCKDOWN) && !(new & REG2_LOCKDOWN)) { > + chip_writeb(flash, cur & ~REG2_LOCKDOWN, lockreg); > + cur = chip_readb(flash, lockreg); > + if ((cur & REG2_LOCKDOWN) == REG2_LOCKDOWN) { > + msg_cwarn("Lockdown can't be removed at 0x%0*" > PRIxPTR "! New value: 0x%02x.\n", > + PRIxPTR_WIDTH, lockreg, cur); > return -1; > } > } > - /* Change read or write lock? */ > - if ((old ^ new_bits) & REG2_RWLOCK) { > + > + /* Change read and/or write bit */ > + if ((cur ^ new) & REG2_RWLOCK) { > /* Do not lockdown yet. */ > - msg_cdbg("Changing locking status at 0x%0*" PRIxPTR " to > 0x%02x\n", PRIxPTR_WIDTH, offset, new_bits & REG2_RWLOCK); > - chip_writeb(flash, new_bits & REG2_RWLOCK, wrprotect); > - if (chip_readb(flash, wrprotect) != (new_bits & > REG2_RWLOCK)) { > - msg_cerr("Locking status change FAILED at 0x%0*" > PRIxPTR "!\n", PRIxPTR_WIDTH, offset); > + uint8_t wanted = (cur & ~REG2_RWLOCK) | (new & > REG2_RWLOCK); > + chip_writeb(flash, wanted, lockreg); > + cur = chip_readb(flash, lockreg); > + if (cur != wanted) { > + msg_cerr("Changing lock bits failed at 0x%0*" > PRIxPTR "! New value: 0x%02x.\n", > + PRIxPTR_WIDTH, lockreg, cur); > return -1; > } > + msg_cdbg("Changed lock bits at 0x%0*" PRIxPTR " to > 0x%02x.\n", > + PRIxPTR_WIDTH, lockreg, cur); > } > - /* Enable lockdown if requested. */ > - if (!(old & REG2_LOCKDOWN) && (new_bits & REG2_LOCKDOWN)) { > - msg_cdbg("Enabling lockdown at 0x%0*" PRIxPTR "\n", > PRIxPTR_WIDTH, offset); > - chip_writeb(flash, new_bits, wrprotect); > - if (chip_readb(flash, wrprotect) != new_bits) { > - msg_cerr("Enabling lockdown FAILED at 0x%0*" > PRIxPTR "!\n", PRIxPTR_WIDTH, offset); > + > + /* Eventually, enable lockdown if requested. */ > + if (!(cur & REG2_LOCKDOWN) && (new & REG2_LOCKDOWN)) { > + chip_writeb(flash, new, lockreg); > + cur = chip_readb(flash, lockreg); > + if (cur != new) { > + msg_cerr("Enabling lockdown FAILED at 0x%0*" > PRIxPTR "! New value: 0x%02x.\n", > + PRIxPTR_WIDTH, lockreg, cur); > return -1; > } > + msg_cdbg("Enabled lockdown at 0x%0*" PRIxPTR ".\n", > PRIxPTR_WIDTH, lockreg); > } > > return 0; > } > > -int unlock_regspace2_block(const struct flashctx *flash, chipaddr off) > +static int unlock_regspace2_block_generic(const struct flashctx *flash, > chipaddr lockreg) > { > - chipaddr wrprotect = flash->virtual_registers + off + 2; > - uint8_t old = chip_readb(flash, wrprotect); > + uint8_t old = chip_readb(flash, lockreg); > /* We don't care for the lockdown bit as long as the RW locks are > 0 after we're done */ > - return changelock_regspace2_block(flash, off, old & ~REG2_RWLOCK); > + return changelock_regspace2_block(flash, lockreg, old, old & > ~REG2_RWLOCK); > } > > static int unlock_regspace2_uniform(struct flashctx *flash, unsigned long > block_size) > { > const unsigned int elems = flash->chip->total_size * 1024 / > block_size; > struct unlockblock blocks[2] = {{.size = block_size, .count = > elems}}; > - return regspace2_walk_unlockblocks(flash, blocks, > &unlock_regspace2_block); > + return regspace2_walk_unlockblocks(flash, blocks, > &unlock_regspace2_block_generic); > } > > int unlock_regspace2_uniform_64k(struct flashctx *flash) > @@ -734,7 +747,7 @@ int unlock_regspace2_block_eraser_0(struct flashctx > *flash) > // FIXME: this depends on the eraseblocks not to be filled up > completely (i.e. to be null-terminated). > const struct unlockblock *unlockblocks = > (const struct unlockblock > *)flash->chip->block_erasers[0].eraseblocks; > - return regspace2_walk_unlockblocks(flash, unlockblocks, > &unlock_regspace2_block); > + return regspace2_walk_unlockblocks(flash, unlockblocks, > &unlock_regspace2_block_generic); > } > > int unlock_regspace2_block_eraser_1(struct flashctx *flash) > @@ -742,6 +755,6 @@ int unlock_regspace2_block_eraser_1(struct flashctx > *flash) > // FIXME: this depends on the eraseblocks not to be filled up > completely (i.e. to be null-terminated). > const struct unlockblock *unlockblocks = > (const struct unlockblock > *)flash->chip->block_erasers[1].eraseblocks; > - return regspace2_walk_unlockblocks(flash, unlockblocks, > &unlock_regspace2_block); > + return regspace2_walk_unlockblocks(flash, unlockblocks, > &unlock_regspace2_block_generic); > } > > -- > Kind regards, Stefan Tauner > >

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[PATCH] Fix handling of write protection at register space address +2.
by Stefan Tauner 20 Dec '14

20 Dec '14

Previously we added the offset of the virtual register in several functions, which produced segfaults. This patch renames a few parameters and reorganizes/fixes various parts of the changelock_regspace2_block() function - hence the rather big diff. Thanks to Roman Lebedev for reporting this issue and testing numerous revisions of this patch. Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> --- $"!%§$&%%$"Q! Third time lucky. Sorry everybody for the spam. chipdrivers.h | 1 - jedec.c | 93 ++++++++++++++++++++++++++++++++++------------------------- 2 files changed, 53 insertions(+), 41 deletions(-) diff --git a/chipdrivers.h b/chipdrivers.h index 8529c74..cac94f3 100644 --- a/chipdrivers.h +++ b/chipdrivers.h @@ -150,7 +150,6 @@ int unlock_regspace2_uniform_32k(struct flashctx *flash); int unlock_regspace2_uniform_64k(struct flashctx *flash); int unlock_regspace2_block_eraser_0(struct flashctx *flash); int unlock_regspace2_block_eraser_1(struct flashctx *flash); -int unlock_regspace2_block(const struct flashctx *flash, chipaddr off); int printlock_regspace2_uniform_64k(struct flashctx *flash); int printlock_regspace2_block_eraser_0(struct flashctx *flash); int printlock_regspace2_block_eraser_1(struct flashctx *flash); diff --git a/jedec.c b/jedec.c index 1345b89..19babf9 100644 --- a/jedec.c +++ b/jedec.c @@ -589,11 +589,10 @@ static int regspace2_walk_unlockblocks(const struct flashctx *flash, const struc #define REG2_LOCKDOWN (1 << 1) #define REG2_MASK (REG2_RWLOCK | REG2_LOCKDOWN) -static int printlock_regspace2_block(const struct flashctx *flash, chipaddr offset) +static int printlock_regspace2_block(const struct flashctx *flash, chipaddr lockreg) { - chipaddr wrprotect = flash->virtual_registers + offset + 2; - uint8_t state = chip_readb(flash, wrprotect); - msg_cdbg("Lock status of block at 0x%0*" PRIxPTR " is ", PRIxPTR_WIDTH, offset); + uint8_t state = chip_readb(flash, lockreg); + msg_cdbg("Lock status of block at 0x%0*" PRIxPTR " is ", PRIxPTR_WIDTH, lockreg); switch (state & REG2_MASK) { case 0: msg_cdbg("Full Access.\n"); @@ -656,67 +655,81 @@ int printlock_regspace2_block_eraser_1(struct flashctx *flash) return regspace2_walk_unlockblocks(flash, unlockblocks, &printlock_regspace2_block); } -static int changelock_regspace2_block(const struct flashctx *flash, chipaddr offset, uint8_t new_bits) -{ - chipaddr wrprotect = flash->virtual_registers + offset + 2; - uint8_t old; - - if (new_bits & ~REG2_MASK) { - msg_cerr("Invalid locking change 0x%02x requested at 0x%0*" PRIxPTR "! " +/* Try to change the lock register at address lockreg from cur to new. + * + * - Try to unlock the lock bit if requested and it is currently set (although this is probably futile). + * - Try to change the read/write bits if requested. + * - Try to set the lockdown bit if requested. + * Return an error immediately if any of this fails. */ +static int changelock_regspace2_block(const struct flashctx *flash, chipaddr lockreg, uint8_t cur, uint8_t new) +{ + /* Only allow changes to known read/write/lockdown bits */ + if (((cur ^ new) & ~REG2_MASK) != 0) { + msg_cerr("Invalid lock change from 0x%02x to 0x%02x requested at 0x%0*" PRIxPTR "!\n" "Please report a bug at flashrom(a)flashrom.org\n", - new_bits, PRIxPTR_WIDTH, offset); + cur, new, PRIxPTR_WIDTH, lockreg); return -1; } - old = chip_readb(flash, wrprotect); - /* Early exist if no change (of read/write/lockdown) was requested. */ - if (((old ^ new_bits) & REG2_MASK) == 0) { - msg_cdbg2("Locking status at 0x%0*" PRIxPTR " not changed\n", PRIxPTR_WIDTH, offset); + + /* Exit early if no change (of read/write/lockdown bits) was requested. */ + if (((cur ^ new) & REG2_MASK) == 0) { + msg_cdbg2("Lock bits at 0x%0*" PRIxPTR " not changed.\n", PRIxPTR_WIDTH, lockreg); return 0; } - /* Normally lockdowns can not be cleared. Try nevertheless if requested. */ - if ((old & REG2_LOCKDOWN) && !(new_bits & REG2_LOCKDOWN)) { - chip_writeb(flash, old & ~REG2_LOCKDOWN, wrprotect); - if (chip_readb(flash, wrprotect) != (old & ~REG2_LOCKDOWN)) { - msg_cerr("Lockdown can't be removed at 0x%0*" PRIxPTR "!\n", PRIxPTR_WIDTH, offset); + + /* Normally the lockdown bit can not be cleared. Try nevertheless if requested. */ + if ((cur & REG2_LOCKDOWN) && !(new & REG2_LOCKDOWN)) { + chip_writeb(flash, cur & ~REG2_LOCKDOWN, lockreg); + cur = chip_readb(flash, lockreg); + if ((cur & REG2_LOCKDOWN) == REG2_LOCKDOWN) { + msg_cwarn("Lockdown can't be removed at 0x%0*" PRIxPTR "! New value: 0x%02x.\n", + PRIxPTR_WIDTH, lockreg, cur); return -1; } } - /* Change read or write lock? */ - if ((old ^ new_bits) & REG2_RWLOCK) { + + /* Change read and/or write bit */ + if ((cur ^ new) & REG2_RWLOCK) { /* Do not lockdown yet. */ - msg_cdbg("Changing locking status at 0x%0*" PRIxPTR " to 0x%02x\n", PRIxPTR_WIDTH, offset, new_bits & REG2_RWLOCK); - chip_writeb(flash, new_bits & REG2_RWLOCK, wrprotect); - if (chip_readb(flash, wrprotect) != (new_bits & REG2_RWLOCK)) { - msg_cerr("Locking status change FAILED at 0x%0*" PRIxPTR "!\n", PRIxPTR_WIDTH, offset); + uint8_t wanted = (cur & ~REG2_RWLOCK) | (new & REG2_RWLOCK); + chip_writeb(flash, wanted, lockreg); + cur = chip_readb(flash, lockreg); + if (cur != wanted) { + msg_cerr("Changing lock bits failed at 0x%0*" PRIxPTR "! New value: 0x%02x.\n", + PRIxPTR_WIDTH, lockreg, cur); return -1; } + msg_cdbg("Changed lock bits at 0x%0*" PRIxPTR " to 0x%02x.\n", + PRIxPTR_WIDTH, lockreg, cur); } - /* Enable lockdown if requested. */ - if (!(old & REG2_LOCKDOWN) && (new_bits & REG2_LOCKDOWN)) { - msg_cdbg("Enabling lockdown at 0x%0*" PRIxPTR "\n", PRIxPTR_WIDTH, offset); - chip_writeb(flash, new_bits, wrprotect); - if (chip_readb(flash, wrprotect) != new_bits) { - msg_cerr("Enabling lockdown FAILED at 0x%0*" PRIxPTR "!\n", PRIxPTR_WIDTH, offset); + + /* Eventually, enable lockdown if requested. */ + if (!(cur & REG2_LOCKDOWN) && (new & REG2_LOCKDOWN)) { + chip_writeb(flash, new, lockreg); + cur = chip_readb(flash, lockreg); + if (cur != new) { + msg_cerr("Enabling lockdown FAILED at 0x%0*" PRIxPTR "! New value: 0x%02x.\n", + PRIxPTR_WIDTH, lockreg, cur); return -1; } + msg_cdbg("Enabled lockdown at 0x%0*" PRIxPTR ".\n", PRIxPTR_WIDTH, lockreg); } return 0; } -int unlock_regspace2_block(const struct flashctx *flash, chipaddr off) +static int unlock_regspace2_block_generic(const struct flashctx *flash, chipaddr lockreg) { - chipaddr wrprotect = flash->virtual_registers + off + 2; - uint8_t old = chip_readb(flash, wrprotect); + uint8_t old = chip_readb(flash, lockreg); /* We don't care for the lockdown bit as long as the RW locks are 0 after we're done */ - return changelock_regspace2_block(flash, off, old & ~REG2_RWLOCK); + return changelock_regspace2_block(flash, lockreg, old, old & ~REG2_RWLOCK); } static int unlock_regspace2_uniform(struct flashctx *flash, unsigned long block_size) { const unsigned int elems = flash->chip->total_size * 1024 / block_size; struct unlockblock blocks[2] = {{.size = block_size, .count = elems}}; - return regspace2_walk_unlockblocks(flash, blocks, &unlock_regspace2_block); + return regspace2_walk_unlockblocks(flash, blocks, &unlock_regspace2_block_generic); } int unlock_regspace2_uniform_64k(struct flashctx *flash) @@ -734,7 +747,7 @@ int unlock_regspace2_block_eraser_0(struct flashctx *flash) // FIXME: this depends on the eraseblocks not to be filled up completely (i.e. to be null-terminated). const struct unlockblock *unlockblocks = (const struct unlockblock *)flash->chip->block_erasers[0].eraseblocks; - return regspace2_walk_unlockblocks(flash, unlockblocks, &unlock_regspace2_block); + return regspace2_walk_unlockblocks(flash, unlockblocks, &unlock_regspace2_block_generic); } int unlock_regspace2_block_eraser_1(struct flashctx *flash) @@ -742,6 +755,6 @@ int unlock_regspace2_block_eraser_1(struct flashctx *flash) // FIXME: this depends on the eraseblocks not to be filled up completely (i.e. to be null-terminated). const struct unlockblock *unlockblocks = (const struct unlockblock *)flash->chip->block_erasers[1].eraseblocks; - return regspace2_walk_unlockblocks(flash, unlockblocks, &unlock_regspace2_block); + return regspace2_walk_unlockblocks(flash, unlockblocks, &unlock_regspace2_block_generic); } -- Kind regards, Stefan Tauner

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flashrom December 2014