flashrom December 2014

flashrom@flashrom.org

27 participants
72 discussions

Re: [flashrom] AT25DF041A PREW tested(with r1850)
by Stefan Tauner 08 Dec '14

08 Dec '14

On Fri, 3 Oct 2014 16:01:16 +0800 Tai-hwa Liang <atliang(a)gmail.com> wrote: > Hi, > > Just want to report successful programming to AT25DF041A with > Flyswatter board(http://www.tincantools.com/JTAG/Flyswatter.html). > > The flash itself is wired to A_TCLK(24)/A_TDI(23)/A_TDO(22)/A_TMS(21) > directly rather than connecting to the JTAG socket(J2) on Flyswatter as > the on board SN74AVC4T245 will require extra output enable signal to > activate, which needs extra flashrom mods. Hello, thanks for your report! I have marked the flash chip as fully tested and will commit that later together with other small changes. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

1 0

Add Eon EN29LV040A
by Denis 'GNUtoo' Carikli 07 Dec '14

07 Dec '14

Hi, This serie is adding the Eon EN29LV040A. It was tested with the following programmer(satasii): 04:06.0 RAID bus controller [0104]: Silicon Image, Inc. PCI0680 Ultra ATA-133 Host Controller [1095:0680] (rev 02) Do I need to send flashrom -VV logs too? Denis.

2 3

[commit] r1857 - trunk
by repository service 07 Dec '14

07 Dec '14

Author: stefanct Date: Sun Dec 7 22:57:53 2014 New Revision: 1857 URL: http://flashrom.org/trac/flashrom/changeset/1857 Log: Add support for Eon EN29LV040 and EN29LV040A. Both use the same ID and are mostly identical. Tested-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Acked-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Modified: trunk/flashchips.c trunk/flashchips.h Modified: trunk/flashchips.c ============================================================================== --- trunk/flashchips.c Fri Dec 5 23:56:13 2014 (r1856) +++ trunk/flashchips.c Sun Dec 7 22:57:53 2014 (r1857) @@ -4863,6 +4863,33 @@ { .vendor = "Eon", + .name = "EN29LV040(A)", + .bustype = BUS_PARALLEL, + .manufacture_id = EON_ID, + .model_id = EON_EN29LV040, + .total_size = 512, + .page_size = 4 * 1024, + .tested = TEST_OK_PREW, + .probe = probe_jedec, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {64 * 1024, 8} }, + .block_erase = erase_sector_jedec, + }, + { + .eraseblocks = { {512 * 1024, 1} }, + .block_erase = erase_chip_block_jedec, + }, + }, + .write = write_jedec_1, + .read = read_memmapped, + .voltage = {3000, 3600}, /* 3.0-3.6V for type -45R and 55R, others 2.7-3.6V */ + }, + + { + .vendor = "Eon", .name = "EN29LV640B", .bustype = BUS_PARALLEL, .manufacture_id = EON_ID, Modified: trunk/flashchips.h ============================================================================== --- trunk/flashchips.h Fri Dec 5 23:56:13 2014 (r1856) +++ trunk/flashchips.h Sun Dec 7 22:57:53 2014 (r1857) @@ -293,7 +293,7 @@ #define EON_EN29F010 0x20 #define EON_EN29F040A 0x7F04 #define EON_EN29LV010 0x7F6E -#define EON_EN29LV040A 0x7F4F /* EN29LV040(A) */ +#define EON_EN29LV040 0x4F /* Same as EN29LV040A */ #define EON_EN29LV640B 0xCB #define EON_EN29F002T 0x7F92 /* Same as EN29F002A */ #define EON_EN29F002B 0x7F97 /* Same as EN29F002AN */

1 0

Re: [flashrom] Success with flashing AOPEN UK79G-1394 (EZ18) -Vw
by Stefan Tauner 07 Dec '14

07 Dec '14

Hello Lawrence, thanks for your report! I have added your board to our list of supported hardware and will commit that later together with other small changes. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

1 0

[PATCH] Support for S25FL127S
by Jernej Škrabec 07 Dec '14

07 Dec '14

Hi! I'm attaching a patch which adds support for Spansion S25FL127S flash chip in 64KiB and 256KiB mode. I also tested 64KiB mode with FT4232H Mini Module which works fine (please see attached logs). Best regards, Jernej Skrabec

2 6

Re: [flashrom] Regression in r1833
by Carl-Daniel Hailfinger 06 Dec '14

06 Dec '14

Hi Roman, thanks for your bug report. On 01.12.2014 21:55, Roman Lebedev wrote: > Hello. > > I had a segfault with current version of flashrom, and with some help > from stefanct at IRC i was able to bisect it down to r1833. > > I attach backtraces. The backtraces were very helpful in determining the bug. Can you please edit jedec.c function static int regspace2_walk_unlockblocks(const struct flashctx *flash, const struct unlockblock *block, unlockblock_func func) The line chipaddr off = flash->virtual_registers + 2; should be replaced with chipaddr off = 0; This is expected to fix the bug. I haven't checked if other places have the same bug, but right now a test of the potential fix would be appreciated. Regards, Carl-Daniel

2 1

[PATCH] Add support for Intel 82599 10G NICs
by Ed Swierk 05 Dec '14

05 Dec '14

The Intel 82599 series of 10G Ethernet controllers has a bit-banged SPI interface that's register-compatible with the one in the 1G controllers, except the register addresses are shifted up by 0x10000. See http://www.intel.com/content/www/us/en/ethernet-controllers/82599-10-gbe-co…. I tested this with a board that has the 0x10fc device and a Micron M25P40 SPI flash chip. I filled in device IDs for other 82599 devices per https://www-ssl.intel.com/content/www/us/en/ethernet-controllers/82599-10-g… and lifted the name strings from the PCI SIG device ID registry. Signed-off-by: Ed Swierk <eswierk(a)skyportsystems.com> =================================================================== diff --git a/trunk/nicintel_spi.c b/trunk/nicintel_spi.c --- a/trunk/nicintel_spi.c (revision 1855) +++ b/trunk/nicintel_spi.c (working copy) @@ -80,6 +80,13 @@ {PCI_VENDOR_ID_INTEL, 0x10b9, OK, "Intel", "82572EI Gigabit Ethernet Controller"}, {PCI_VENDOR_ID_INTEL, 0x10d3, OK, "Intel", "82574L Gigabit Ethernet Controller"}, + {PCI_VENDOR_ID_INTEL, 0x10f7, NT, "Intel", "10 Gigabit BR KX4 Dual Port Network Connection"}, + {PCI_VENDOR_ID_INTEL, 0x10f8, NT, "Intel", "82599 10 Gigabit Dual Port Backplane Connection"}, + {PCI_VENDOR_ID_INTEL, 0x10f9, NT, "Intel", "82599 10 Gigabit Dual Port Network Connection"}, + {PCI_VENDOR_ID_INTEL, 0x10fb, NT, "Intel", "82599ES 10-Gigabit SFI/SFP+ Network Connection"}, + {PCI_VENDOR_ID_INTEL, 0x10fc, OK, "Intel", "82599 10 Gigabit Dual Port Network Connection"}, + {PCI_VENDOR_ID_INTEL, 0x1557, NT, "Intel", "82599 10 Gigabit Network Connection"}, + {0}, }; @@ -183,7 +190,13 @@ if (!io_base_addr) return 1; - nicintel_spibar = rphysmap("Intel Gigabit NIC w/ SPI flash", io_base_addr, MEMMAP_SIZE); + if (dev->device_id < 0x10f0) { + nicintel_spibar = rphysmap("Intel Gigabit NIC w/ SPI flash", io_base_addr, + MEMMAP_SIZE); + } else { + nicintel_spibar = rphysmap("Intel 10 Gigabit NIC w/ SPI flash", io_base_addr + 0x10000, + MEMMAP_SIZE); + } if (nicintel_spibar == ERROR_PTR) return 1;

2 1

[commit] r1856 - trunk
by repository service 05 Dec '14

05 Dec '14

Author: stefanct Date: Fri Dec 5 23:56:13 2014 New Revision: 1856 URL: http://flashrom.org/trac/flashrom/changeset/1856 Log: Add support for Intel 82599 10 GbE NICs. The Intel 82599 series of 10 GbE controllers has a bit-banged SPI interface that's register-compatible with the one in the 1 GbE controllers, except the register addresses are shifted up by 0x10000, cf. Intel document 331520: http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/8259… This patch was tested with a board that has the 0x10fc device and a Micron M25P40 SPI flash chip. The PCI IDs and names for the devices are per Intel document 331521 https://www-ssl.intel.com/content/dam/www/public/us/en/documents/specificat… and the PCI SIG device ID registry with small refinements. Signed-off-by: Ed Swierk <eswierk(a)skyportsystems.com> Signed-off-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner(a)alumni.tuwien.ac.at> Modified: trunk/nicintel_spi.c Modified: trunk/nicintel_spi.c ============================================================================== --- trunk/nicintel_spi.c Sun Nov 30 23:31:12 2014 (r1855) +++ trunk/nicintel_spi.c Fri Dec 5 23:56:13 2014 (r1856) @@ -29,6 +29,9 @@ * * Intel 82574 Gigabit Ethernet Controller Family Datasheet * http://www.intel.com/content/www/us/en/ethernet-controllers/82574l-gbe-cont… + * + * Intel 82599 10 GbE Controller Datasheet (331520) + * http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/8259… */ #include <stdlib.h> @@ -50,7 +53,7 @@ * Table 13-6 * * Bit 04, 05: FWE (Flash Write Enable Control) - * 00b = not allowed + * 00b = not allowed (on some cards this sends an erase command if bit 31 (FL_ER) of FLA is set) * 01b = flash writes disabled * 10b = flash writes enabled * 11b = not allowed @@ -80,6 +83,18 @@ {PCI_VENDOR_ID_INTEL, 0x10b9, OK, "Intel", "82572EI Gigabit Ethernet Controller"}, {PCI_VENDOR_ID_INTEL, 0x10d3, OK, "Intel", "82574L Gigabit Ethernet Controller"}, + {PCI_VENDOR_ID_INTEL, 0x10d8, NT, "Intel", "82599 10 Gigabit Unprogrammed Network Controller"}, + {PCI_VENDOR_ID_INTEL, 0x10f7, NT, "Intel", "82599 10 Gigabit KX4 Dual Port Network Controller"}, + {PCI_VENDOR_ID_INTEL, 0x10f8, NT, "Intel", "82599 10 Gigabit Dual Port Backplane Controller"}, + {PCI_VENDOR_ID_INTEL, 0x10f9, NT, "Intel", "82599 10 Gigabit CX4 Dual Port Network Controller"}, + {PCI_VENDOR_ID_INTEL, 0x10fb, NT, "Intel", "82599 10-Gigabit SFI/SFP+ Network Controller"}, + {PCI_VENDOR_ID_INTEL, 0x10fc, OK, "Intel", "82599 10 Gigabit XAUI/BX4 Dual Port Network Controller"}, + {PCI_VENDOR_ID_INTEL, 0x1517, NT, "Intel", "82599 10 Gigabit KR Network Controller"}, + {PCI_VENDOR_ID_INTEL, 0x151c, NT, "Intel", "82599 10 Gigabit TN Network Controller"}, + {PCI_VENDOR_ID_INTEL, 0x1529, NT, "Intel", "82599 10 Gigabit Dual Port Network Controller with FCoE"}, + {PCI_VENDOR_ID_INTEL, 0x152a, NT, "Intel", "82599 10 Gigabit Dual Port Backplane Controller with FCoE"}, + {PCI_VENDOR_ID_INTEL, 0x1557, NT, "Intel", "82599 10 Gigabit SFI Network Controller"}, + {0}, }; @@ -183,7 +198,13 @@ if (!io_base_addr) return 1; - nicintel_spibar = rphysmap("Intel Gigabit NIC w/ SPI flash", io_base_addr, MEMMAP_SIZE); + if (dev->device_id < 0x10d8) { + nicintel_spibar = rphysmap("Intel Gigabit NIC w/ SPI flash", io_base_addr, + MEMMAP_SIZE); + } else { + nicintel_spibar = rphysmap("Intel 10 Gigabit NIC w/ SPI flash", io_base_addr + 0x10000, + MEMMAP_SIZE); + } if (nicintel_spibar == ERROR_PTR) return 1;

1 0

updating Coreboot
by Mathilde 05 Dec '14

05 Dec '14

Hello, Being not an informatician, I need help for updating my BIOS Coreboot (on a Thinkpad X60), because of heat issues. I dowloaded the last release here http://libreboot.org/docs/release.html, and installed the build dependencies. Could you explain me step by step what to do now? I did'nt understand whether I am to compile flashrom or not. In advance thank you very much! Math

1 0

Winbond 25Q256 support
by Francisco Javier Lasa Gutierrez 02 Dec '14

02 Dec '14

I need to program a 25Q256 chip, do you plan to add support to this EEPROM? if not, can you please guide me how to add it to the code?

2 1

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

flashrom December 2014