flashrom May 2013

flashrom@flashrom.org

30 participants
97 discussions

Re: [flashrom] Added chipsets
by Николай Николаев 28 May '13

28 May '13

---------- Forwarded message ---------- From: Николай Николаев <evrinoma(a)gmail.com> Date: 2013/5/28 Subject: Re: [flashrom] Added chipsets To: Steven Zakulec <spzakulec(a)gmail.com> Hi Steven, Other people can provide more details on the general case, but in this > instance, with only a WREN instruction, the FEATURE line should be: > I've been informed by others that your original idea of dropping the > FEATURE line is actually correct, so you should do that instead of what I > proposed. > i dropped this line because this line for chips fetch Numonyx N25Q00AA13- >>> I'll admit I don't really know how this chip works, but it seems there >>> should be a 3rd eraseblock from the description of the memory organization >>> (datasheet is Rev E, 2/12): >>> >>> Memory Configuration and Block Diagram >>> The memory is a stacked device comprised of four 256Mb chips. Each chip >>> is internally >>> partitioned into two 128Mb segments. Each page of memory can be >>> individually pro- >>> grammed. Bits are programmed from one through zero. The device is >>> subsector, sector, >>> or single 256Mb chip erasable, but not page-erasable. Bits are erased >>> from zero through >>> one. The memory is configured as 134,217,728 bytes (8 bits each); 2048 >>> sectors (64KB >>> each); 32,768 subsectors (4KB each); and 524,288 pages (256 bytes each); >>> and 64 OTP >>> bytes are located outside the main memory array. >>> >>> You've got: >>> + .eraseblocks = { {4 * 1024, 32768 } }, >>> + .block_erase = spi_block_erase_20, >>> + }, { >>> + .eraseblocks = { {64 * 1024, 2048 } }, >>> + .block_erase = spi_block_erase_d8, >>> >>> There's a die erase opcode, which I am unfamiliar with- maybe it handles >>> erasing a single 256Mb chip at a time? >>> >> >> You right this chip used a four 256 Mb chips. And 256 Mb chip has a three >> instruction subsector 20(hex) sector D8(hex) bulk C7(hex) erase commands. >> But chip N25Q00AA13 has a other op-code to initiate die erase command >> C4 (hex) >> >> So, how do you do a single-chip erase for this chip? > I think this function is feature, because use "not general" op-code C4 for die erase command. Also first we need to write a special function feature extended addressing for chips more than 128 mb, after that we will think about how to initiate die erase instruction. What data sheets do you have for those chips? The ones below list the > small sector erase op-code as D7. > LE25FW418A: 61709 SY 20090428-S00004 No.A1432 > LE25FW808: 61009 SY IM 20090319-S00003 No.A0839 > LE25FW806: 70208 SY IM 20070628-S00004 No.A0838 > I have a equivalence data sheets. LE25FW808 has a general op-code 20(hex) to initiate small sector erase. Other chips use a feature op-code as D7. -- With best regards Nikolay Nikolaev -- With best regards Nikolay Nikolaev С Уважением Николаев Николай

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Re: [flashrom] Added chipsets
by Николай Николаев 28 May '13

28 May '13

---------- Forwarded message ---------- From: Николай Николаев <evrinoma(a)gmail.com> Date: 2013/5/27 Subject: Re: [flashrom] Added chipsets To: Steven Zakulec <spzakulec(a)gmail.com> Hi steven, 2013/5/27 Steven Zakulec <spzakulec(a)gmail.com> > Before I get started on the review, just a general comment or two. > If you plan to contribute in the future (which I certainly hope you will), > please break submissions down into blocks of 5-10 chips. This makes it so > much easier for me, and any other reviewers, to quickly check the patch and > provide feedback in a timely manner. > Sorry, this is my first patch. My next patch i wrote with you wish. ( http://patchwork.coreboot.org/patch/3896/) 8) > In the last review, I mentioned the Numonyx M45PE series (10, 20, 40, 80, > 16), should only have > + .feature_bits = FEATURE_WRSR_WREN, > set when the command is there. It appears I may have been unclear there, > because instead of removing just the WREN flag, you removed the whole line > (the chips do have a Write Status Register- WRSR). > > Continuing the review from Numonyx M45PE16. > Sorry i don't know which flag must be used. You right these chips have a only WREN instruction, and i think if these chips doesn't have a feature that i exclude feature_bits. Maybe we will be able to specify the details. > Numonyx M25PX80- > + .voltage = {2700, 3600}, > The datasheets I've seen have it as 2.3-3.6V (rev 4 Dec 2008 and Rev B > 3/2013) > > + .tested = TEST_OK_PREW, > Unless I'm reading it wrong, it looks like you're adding this chip as a > fully tested one- would you mind supplying some logs showing that it > successfully does these operations? (write logs shouldn't contain all :S > (for skipped blocks) next to the addresses). > You right this is my typos, and i fixed them. > Numonyx N25Q00AA13- > I'll admit I don't really know how this chip works, but it seems there > should be a 3rd eraseblock from the description of the memory organization > (datasheet is Rev E, 2/12): > > Memory Configuration and Block Diagram > The memory is a stacked device comprised of four 256Mb chips. Each chip is > internally > partitioned into two 128Mb segments. Each page of memory can be > individually pro- > grammed. Bits are programmed from one through zero. The device is > subsector, sector, > or single 256Mb chip erasable, but not page-erasable. Bits are erased from > zero through > one. The memory is configured as 134,217,728 bytes (8 bits each); 2048 > sectors (64KB > each); 32,768 subsectors (4KB each); and 524,288 pages (256 bytes each); > and 64 OTP > bytes are located outside the main memory array. > > You've got: > + .eraseblocks = { {4 * 1024, 32768 } }, > + .block_erase = spi_block_erase_20, > + }, { > + .eraseblocks = { {64 * 1024, 2048 } }, > + .block_erase = spi_block_erase_d8, > > There's a die erase opcode, which I am unfamiliar with- maybe it handles > erasing a single 256Mb chip at a time? > You right this chip used a four 256 Mb chips. And 256 Mb chip has a three instruction subsector 20(hex) sector D8(hex) bulk C7(hex) erase commands. But chip N25Q00AA13 has a other op-code to initiate die erase command C4 (hex) > Sanyo LF25FW203A / LE25FW203A- > Thanks so much for getting to the bottom of this chip, and figuring out > which chip it actually is. > > .probe = probe_spi_rdid, > Maybe I'm reading the patch wrong, but you appear to be missing the > .probe_timing line for this chip. > You reading patch wrong. The probe_timing line for this chip is present below in source code. > LE25FW418A, LE25FW808 and LE25FW806 - > For the LE25FW806A you included the small sector erase, but left it out > for the rest of the chips- any particular reason for this? > Because only LE25FW806A has a small sector erase op-code instruction, other chips didn't have it. > > I'll cover from Spansion S25FL128S to the end tomorrow. > Excellent how to delete all versions of the patch and leave only comments in one thread? I send a new version patch -- With best regards Nikolay Nikolaev С Уважением Николаев Николай -- With best regards Nikolay Nikolaev С Уважением Николаев Николай

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Failing to write flash to Abit AN-M2HD motherboard
by Jon Wickström 27 May '13

27 May '13

Hi, Here is some more info regarding my last email. Writing the new flash image failed. Before that I read the old and verified it with flashrom. //Jonte --8<--- $ sudo flashrom -v bios_old_2013-05-26.bin flashrom v0.9.5.2-r1517 on Linux 3.2.0-44-generic (x86_64), built with libpci 3.1.8, GCC 4.6.3, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found chipset "NVIDIA MCP67". Enabling flash write... This chipset is not really supported yet. Guesswork... Please send the output of "flashrom -V" to flashrom(a)flashrom.org with your board name: flashrom -V as the subject to help us finish support for your chipset. Thanks. OK. Found PMC flash chip "Pm49FL004" (512 kB, LPC, FWH) at physical address 0xfff80000. Flash image seems to be a legacy BIOS. Disabling coreboot-related checks. Reading old flash chip contents... done. Verifying flash... VERIFIED. jonte@wintermute:/home/jonte$ sudo flashrom -w /mnt/floppy/abit/ ABITFAE.BAT AWDFLASH.EXE M628A_20.BIN M628A_20.TXT RUNME.BAT jonte@wintermute:/home/jonte$ sudo flashrom -w /mnt/floppy/abit/M628A_20.BIN flashrom v0.9.5.2-r1517 on Linux 3.2.0-44-generic (x86_64), built with libpci 3.1.8, GCC 4.6.3, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. Found chipset "NVIDIA MCP67". Enabling flash write... This chipset is not really supported yet. Guesswork... Please send the output of "flashrom -V" to flashrom(a)flashrom.org with your board name: flashrom -V as the subject to help us finish support for your chipset. Thanks. OK. Found PMC flash chip "Pm49FL004" (512 kB, LPC, FWH) at physical address 0xfff80000. Flash image seems to be a legacy BIOS. Disabling coreboot-related checks. Reading old flash chip contents... done. Erasing and writing flash chip... ERASE FAILED at 0x00000000! Expected=0xff, Read=0x49, failed byte count from 0x00000000-0x00000fff: 0x6ee ERASE FAILED! Reading current flash chip contents... done. ERASE FAILED at 0x00000000! Expected=0xff, Read=0x49, failed byte count from 0x00000000-0x0000ffff: 0x6ee ERASE FAILED! Reading current flash chip contents... done. ERASE FAILED at 0x00000000! Expected=0xff, Read=0x49, failed byte count from 0x00000000-0x0007ffff: 0x5f21f ERASE FAILED! FAILED! Uh oh. Erase/write failed. Checking if anything changed. Good. It seems nothing was changed. Writing to the flash chip apparently didn't do anything. This means we have to add special support for your board, programmer or flash chip. Please report this on IRC at irc.freenode.net (channel #flashrom) or mail flashrom(a)flashrom.org! ------------------------------------------------------------------------------- You may now reboot or simply leave the machine running. -- jonte(a)xn--wickstrm-t4a.fi

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Flashrom advised to email!
by Eamon M 27 May '13

27 May '13

Hi, Flashrom advised to email. Flashing 2048k bios rom file to a Lanner FW-8750 motherboard gave the following error as attached. Any help would be gratefully received. Regards, Eamon

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Re: [flashrom] Added chipsets
by Steven Zakulec 27 May '13

27 May '13

On Mon, May 27, 2013 at 12:02 PM, Steven Zakulec <spzakulec(a)gmail.com>wrote: > > > > On Mon, May 27, 2013 at 5:25 AM, Николай Николаев <evrinoma(a)gmail.com>wrote: > >> Hi steven, >> >> 2013/5/27 Steven Zakulec <spzakulec(a)gmail.com> >>> >>> In the last review, I mentioned the Numonyx M45PE series (10, 20, 40, >>> 80, 16), should only have >>> + .feature_bits = FEATURE_WRSR_WREN, >>> set when the command is there. It appears I may have been unclear >>> there, because instead of removing just the WREN flag, you removed the >>> whole line (the chips do have a Write Status Register- WRSR). >>> >> >>> Continuing the review from Numonyx M45PE16. >>> >> Sorry i don't know which flag must be used. You right these chips have a >> only WREN instruction, and i think if these chips doesn't have a feature >> that i exclude feature_bits. Maybe we will be able to specify the details. >> > Other people can provide more details on the general case, but in this > instance, with only a WREN instruction, the FEATURE line should be: > + .feature_bits = FEATURE_WRSR > > I've been informed by others that your original idea of dropping the FEATURE line is actually correct, so you should do that instead of what I proposed.

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Re: [flashrom] Added chipsets
by Steven Zakulec 27 May '13

27 May '13

On Mon, May 27, 2013 at 5:25 AM, Николай Николаев <evrinoma(a)gmail.com>wrote: > Hi steven, > > 2013/5/27 Steven Zakulec <spzakulec(a)gmail.com> > >> Before I get started on the review, just a general comment or two. >> If you plan to contribute in the future (which I certainly hope you >> will), please break submissions down into blocks of 5-10 chips. This makes >> it so much easier for me, and any other reviewers, to quickly check the >> patch and provide feedback in a timely manner. >> > Sorry, this is my first patch. My next patch i wrote with you wish. ( > http://patchwork.coreboot.org/patch/3896/) 8) > > > >> In the last review, I mentioned the Numonyx M45PE series (10, 20, 40, 80, >> 16), should only have >> + .feature_bits = FEATURE_WRSR_WREN, >> set when the command is there. It appears I may have been unclear there, >> because instead of removing just the WREN flag, you removed the whole line >> (the chips do have a Write Status Register- WRSR). >> > >> Continuing the review from Numonyx M45PE16. >> > Sorry i don't know which flag must be used. You right these chips have a > only WREN instruction, and i think if these chips doesn't have a feature > that i exclude feature_bits. Maybe we will be able to specify the details. > Other people can provide more details on the general case, but in this instance, with only a WREN instruction, the FEATURE line should be: + .feature_bits = FEATURE_WRSR > > >> Numonyx M25PX80- >> + .voltage = {2700, 3600}, >> The datasheets I've seen have it as 2.3-3.6V (rev 4 Dec 2008 and Rev B >> 3/2013) >> >> + .tested = TEST_OK_PREW, >> Unless I'm reading it wrong, it looks like you're adding this chip as a >> fully tested one- would you mind supplying some logs showing that it >> successfully does these operations? (write logs shouldn't contain all :S >> (for skipped blocks) next to the addresses). >> > You right this is my typos, and i fixed them. > > >> Numonyx N25Q00AA13- >> I'll admit I don't really know how this chip works, but it seems there >> should be a 3rd eraseblock from the description of the memory organization >> (datasheet is Rev E, 2/12): >> >> Memory Configuration and Block Diagram >> The memory is a stacked device comprised of four 256Mb chips. Each chip >> is internally >> partitioned into two 128Mb segments. Each page of memory can be >> individually pro- >> grammed. Bits are programmed from one through zero. The device is >> subsector, sector, >> or single 256Mb chip erasable, but not page-erasable. Bits are erased >> from zero through >> one. The memory is configured as 134,217,728 bytes (8 bits each); 2048 >> sectors (64KB >> each); 32,768 subsectors (4KB each); and 524,288 pages (256 bytes each); >> and 64 OTP >> bytes are located outside the main memory array. >> >> You've got: >> + .eraseblocks = { {4 * 1024, 32768 } }, >> + .block_erase = spi_block_erase_20, >> + }, { >> + .eraseblocks = { {64 * 1024, 2048 } }, >> + .block_erase = spi_block_erase_d8, >> >> There's a die erase opcode, which I am unfamiliar with- maybe it handles >> erasing a single 256Mb chip at a time? >> > > You right this chip used a four 256 Mb chips. And 256 Mb chip has a three > instruction subsector 20(hex) sector D8(hex) bulk C7(hex) erase commands. > But chip N25Q00AA13 has a other op-code to initiate die erase command > C4 (hex) > > So, how do you do a single-chip erase for this chip? > > >> Sanyo LF25FW203A / LE25FW203A- >> Thanks so much for getting to the bottom of this chip, and figuring out >> which chip it actually is. >> >> .probe = probe_spi_rdid, >> Maybe I'm reading the patch wrong, but you appear to be missing the >> .probe_timing line for this chip. >> > You reading patch wrong. The probe_timing line for this chip is present > below in source code. > Okay- thanks for checking. > > >> LE25FW418A, LE25FW808 and LE25FW806 - >> For the LE25FW806A you included the small sector erase, but left it out >> for the rest of the chips- any particular reason for this? >> > Because only LE25FW806A has a small sector erase op-code instruction, > other chips didn't have it. > > What data sheets do you have for those chips? The ones below list the small sector erase op-code as D7. LE25FW418A: 61709 SY 20090428-S00004 No.A1432 LE25FW808: 61009 SY IM 20090319-S00003 No.A0839 LE25FW806: 70208 SY IM 20070628-S00004 No.A0838 >> >> I'll cover from Spansion S25FL128S to the end tomorrow. >> > Excellent > > > how to delete all versions of the patch and leave only comments in one > thread? > Don't change what you're doing for this patch. > > I send a new version patch > > -- > With best regards Nikolay Nikolaev > С Уважением Николаев Николай >

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Re: [flashrom] Added chipsets
by Steven Zakulec 27 May '13

27 May '13

Before I get started on the review, just a general comment or two. If you plan to contribute in the future (which I certainly hope you will), please break submissions down into blocks of 5-10 chips. This makes it so much easier for me, and any other reviewers, to quickly check the patch and provide feedback in a timely manner. In the last review, I mentioned the Numonyx M45PE series (10, 20, 40, 80, 16), should only have + .feature_bits = FEATURE_WRSR_WREN, set when the command is there. It appears I may have been unclear there, because instead of removing just the WREN flag, you removed the whole line (the chips do have a Write Status Register- WRSR). Continuing the review from Numonyx M45PE16. Numonyx M25PX80- + .voltage = {2700, 3600}, The datasheets I've seen have it as 2.3-3.6V (rev 4 Dec 2008 and Rev B 3/2013) + .tested = TEST_OK_PREW, Unless I'm reading it wrong, it looks like you're adding this chip as a fully tested one- would you mind supplying some logs showing that it successfully does these operations? (write logs shouldn't contain all :S (for skipped blocks) next to the addresses). Numonyx N25Q00AA13- I'll admit I don't really know how this chip works, but it seems there should be a 3rd eraseblock from the description of the memory organization (datasheet is Rev E, 2/12): Memory Configuration and Block Diagram The memory is a stacked device comprised of four 256Mb chips. Each chip is internally partitioned into two 128Mb segments. Each page of memory can be individually pro- grammed. Bits are programmed from one through zero. The device is subsector, sector, or single 256Mb chip erasable, but not page-erasable. Bits are erased from zero through one. The memory is configured as 134,217,728 bytes (8 bits each); 2048 sectors (64KB each); 32,768 subsectors (4KB each); and 524,288 pages (256 bytes each); and 64 OTP bytes are located outside the main memory array. You've got: + .eraseblocks = { {4 * 1024, 32768 } }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {64 * 1024, 2048 } }, + .block_erase = spi_block_erase_d8, There's a die erase opcode, which I am unfamiliar with- maybe it handles erasing a single 256Mb chip at a time? Sanyo LF25FW203A / LE25FW203A- Thanks so much for getting to the bottom of this chip, and figuring out which chip it actually is. .probe = probe_spi_rdid, Maybe I'm reading the patch wrong, but you appear to be missing the .probe_timing line for this chip. LE25FW418A, LE25FW808 and LE25FW806 - For the LE25FW806A you included the small sector erase, but left it out for the rest of the chips- any particular reason for this? I'll cover from Spansion S25FL128S to the end tomorrow. On Tue, May 21, 2013 at 4:29 AM, Николай Николаев <evrinoma(a)gmail.com>wrote: > A new version patch > > Was checked: > -functions block erase for all chips > -feature bits for all chips > -model_id for all chips > -manufacture_id for all chips > -voltage for all chips > > -- > With best regards Nikolay Nikolaev > С Уважением Николаев Николай > > _______________________________________________ > flashrom mailing list > flashrom(a)flashrom.org > http://www.flashrom.org/mailman/listinfo/flashrom >

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Abit AN-M2HD
by Jon Wickström 26 May '13

26 May '13

Hi, I mailed you earlier today regarding my Abit AN-M2HD main board. I think there are different revisions of this board, I don't know which I have. I was asked on irc to provide the following: flashrom -p internal -V http://paste.flashrom.org/view.php?id=1646 lcpci -nnvvvxxx http://paste.flashrom.org/view.php?id=1647 superiotool -deV http://paste.flashrom.org/view.php?id=1648 flashrom -p internal -r readout.rom http://paste.flashrom.org/view.php?id=1649 I assume it will be some time before somebody has time to look at this, so I will try forcing the flash with abits own flash utility. Supposedly this is a bug in the BIOS. With best regards, //Jonte -- jonte(a)xn--wickstrm-t4a.fi

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Board Abit AN-M2HD
by Jon Wickström 26 May '13

26 May '13

Hi, I find it a bit interesting the board specifies MCP68, but the chipset found is MCP67. I tried to flash the board from a dos boot image (via grub), but got the error that the flash is write protected. It seems forcing the write worked for somebody: http://www.technologicalwanderings.co.uk/node/70 I have not tried that. //Jonte --8<--- $ sudo flashrom -V flashrom v0.9.5.2-r1517 on Linux 3.2.0-44-generic (x86_64), built with libpci 3.1.8, GCC 4.6.3, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 696M loops per second, 10 myus = 11 us, 100 myus = 100 us, 1000 myus = 1003 us, 10000 myus = 9958 us, 4 myus = 5 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "Unknow" DMI string system-product-name: "Unknow" DMI string system-version: "Unknow" DMI string baseboard-manufacturer: "nVIDIA" DMI string baseboard-product-name: "AN-M2HD(MCP68)" DMI string baseboard-version: "1.x " DMI string chassis-type: "Desktop" Found chipset "NVIDIA MCP67" with PCI ID 10de:0548. Enabling flash write... This chipset is not really supported yet. Guesswork... ISA/LPC bridge reg 0x8a contents: 0x00, bit 6 is 0, bit 5 is 0 Flash bus type is LPC Found SMBus device 10de:0542 at 00:01:1 MCP SPI BAR is at 0x00000000 MCP SPI is not used. Please send the output of "flashrom -V" to flashrom(a)flashrom.org with your board name: flashrom -V as the subject to help us finish support for your chipset. Thanks. OK. The following protocols are supported: LPC. Probing for AMIC A49LF040A, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0x4c, id2 0x37, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Found PMC flash chip "Pm49FL004" (512 kB, LPC, FWH) at physical address 0xfff80000. Probing for SST SST49LF020, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF020A, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF040, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF040B, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for SST SST49LF080A, 1024 kB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF160C, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0x49, id2 0x4d, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50LPW116, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040A, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39V040B, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39V040C, 512 kB: probe_jedec_common: id1 0x9d, id2 0x6e Probing for Winbond W39V080A, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002A, 256 kB: probe_jedec_common: id1 0x9d, id2 0x6e Found PMC flash chip "Pm49FL004" (512 kB, LPC, FWH). No operations were specified. Restoring PCI config space for 00:01:0 reg 0x6d Restoring PCI config space for 00:01:0 reg 0x90 Restoring PCI config space for 00:01:0 reg 0x8c Restoring PCI config space for 00:01:0 reg 0x88

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flashrom verbose log
by Andrew Butterworth 25 May '13

25 May '13

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flashrom May 2013