flashrom May 2013

flashrom@flashrom.org

30 participants
97 discussions

[PATCH] Remove exit call from sys_physmap_*
by Niklas Söderlund 13 Sep '13

13 Sep '13

All callers are prepared to handle error if ERROR_PTR is returned. Signed-off-by: Niklas Söderlund <niso(a)kth.se> --- physmap.c | 15 ++++++--------- 1 file changed, 6 insertions(+), 9 deletions(-) diff --git a/physmap.c b/physmap.c index 5aa9874..adce315 100644 --- a/physmap.c +++ b/physmap.c @@ -173,12 +173,11 @@ static void *sys_physmap_rw_uncached(unsigned long phys_addr, size_t len) /* Open the memory device UNCACHED. Important for MMIO. */ if (-1 == (fd_mem = open(MEM_DEV, O_RDWR | O_SYNC))) { perror("Critical error: open(" MEM_DEV ")"); - exit(2); + return ERROR_PTR; } } - virt_addr = mmap(NULL, len, PROT_WRITE | PROT_READ, MAP_SHARED, - fd_mem, (off_t)phys_addr); + virt_addr = mmap(NULL, len, PROT_WRITE | PROT_READ, MAP_SHARED, fd_mem, (off_t)phys_addr); return MAP_FAILED == virt_addr ? ERROR_PTR : virt_addr; } @@ -192,14 +191,12 @@ static void *sys_physmap_ro_cached(unsigned long phys_addr, size_t len) if (-1 == fd_mem_cached) { /* Open the memory device CACHED. */ if (-1 == (fd_mem_cached = open(MEM_DEV, O_RDWR))) { - msg_perr("Critical error: open(" MEM_DEV "): %s", - strerror(errno)); - exit(2); + msg_perr("Critical error: open(" MEM_DEV "): %s", strerror(errno)); + return ERROR_PTR; } } - virt_addr = mmap(NULL, len, PROT_READ, MAP_SHARED, - fd_mem_cached, (off_t)phys_addr); + virt_addr = mmap(NULL, len, PROT_READ, MAP_SHARED, fd_mem_cached, (off_t)phys_addr); return MAP_FAILED == virt_addr ? ERROR_PTR : virt_addr; } @@ -209,7 +206,7 @@ void physunmap(void *virt_addr, size_t len) msg_pspew("Not unmapping zero size at %p\n", virt_addr); return; } - + munmap(virt_addr, len); } #endif -- 1.7.12.3

2 1

[PATCH 1/5] rayer_spi: Create list of programmer types
by Kyösti Mälkki 28 Aug '13

28 Aug '13

Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- rayer_spi.c | 106 ++++++++++++++++++++++++++++++++++-------------------------- 1 file changed, 61 insertions(+), 45 deletions(-) diff --git a/rayer_spi.c b/rayer_spi.c index b312610..b4ef205 100644 --- a/rayer_spi.c +++ b/rayer_spi.c @@ -37,21 +37,48 @@ #include "programmer.h" #include "hwaccess.h" -enum rayer_type { - TYPE_RAYER, - TYPE_XILINX_DLC5, -}; - /* We have two sets of pins, out and in. The numbers for both sets are * independent and are bitshift values, not real pin numbers. * Default settings are for the RayeR hardware. */ -/* Pins for master->slave direction */ -static int rayer_cs_bit = 5; -static int rayer_sck_bit = 6; -static int rayer_mosi_bit = 7; -/* Pins for slave->master direction */ -static int rayer_miso_bit = 6; + +struct rayer_programmer { + const char * type; + const enum test_state status; + const char * description; + const void * private; +}; + +struct rayer_pinout { + int cs_bit; + int sck_bit; + int mosi_bit; + int miso_bit; + void (*preinit)(void *); + int (*shutdown)(void *); +}; + +static struct rayer_pinout rayer_spipgm = { + .cs_bit = 5, + .sck_bit = 6, + .mosi_bit = 7, + .miso_bit = 6, +}; + +static struct rayer_pinout xilinx_dlc5 = { + .cs_bit = 2, + .sck_bit = 1, + .mosi_bit = 0, + .miso_bit = 4, +}; + +struct rayer_programmer rayer_spi_types[] = { + {"rayer", NT, "RayeR SPIPGM", &rayer_spipgm}, + {"xilinx", NT, "Xilinx Parallel Cable III (DLC 5)", &xilinx_dlc5}, + {0}, +}; + +struct rayer_pinout *pinout = NULL; static uint16_t lpt_iobase; @@ -60,22 +87,22 @@ static uint8_t lpt_outbyte; static void rayer_bitbang_set_cs(int val) { - lpt_outbyte &= ~(1 << rayer_cs_bit); - lpt_outbyte |= (val << rayer_cs_bit); + lpt_outbyte &= ~(1 << pinout->cs_bit); + lpt_outbyte |= (val << pinout->cs_bit); OUTB(lpt_outbyte, lpt_iobase); } static void rayer_bitbang_set_sck(int val) { - lpt_outbyte &= ~(1 << rayer_sck_bit); - lpt_outbyte |= (val << rayer_sck_bit); + lpt_outbyte &= ~(1 << pinout->sck_bit); + lpt_outbyte |= (val << pinout->sck_bit); OUTB(lpt_outbyte, lpt_iobase); } static void rayer_bitbang_set_mosi(int val) { - lpt_outbyte &= ~(1 << rayer_mosi_bit); - lpt_outbyte |= (val << rayer_mosi_bit); + lpt_outbyte &= ~(1 << pinout->mosi_bit); + lpt_outbyte |= (val << pinout->mosi_bit); OUTB(lpt_outbyte, lpt_iobase); } @@ -83,8 +110,8 @@ static int rayer_bitbang_get_miso(void) { uint8_t tmp; - tmp = INB(lpt_iobase + 1); - tmp = (tmp >> rayer_miso_bit) & 0x1; + tmp = INB(lpt_iobase + 1) ^ 0x80; // bit.7 inverted + tmp = (tmp >> pinout->miso_bit) & 0x1; return tmp; } @@ -99,8 +126,8 @@ static const struct bitbang_spi_master bitbang_spi_master_rayer = { int rayer_spi_init(void) { + struct rayer_programmer *prog = rayer_spi_types; char *arg = NULL; - enum rayer_type rayer_type = TYPE_RAYER; /* Non-default port requested? */ arg = extract_programmer_param("iobase"); @@ -138,36 +165,20 @@ int rayer_spi_init(void) arg = extract_programmer_param("type"); if (arg) { - if (!strcasecmp(arg, "rayer")) { - rayer_type = TYPE_RAYER; - } else if (!strcasecmp(arg, "xilinx")) { - rayer_type = TYPE_XILINX_DLC5; - } else { + for (; prog->type; ++prog) { + if (! strcasecmp (arg, prog->type)) { + break; + } + } + if(! prog->type) { msg_perr("Error: Invalid device type specified.\n"); free(arg); return 1; } + free(arg); } - free(arg); - switch (rayer_type) { - case TYPE_RAYER: - msg_pdbg("Using RayeR SPIPGM pinout.\n"); - /* Bits for master->slave direction */ - rayer_cs_bit = 5; - rayer_sck_bit = 6; - rayer_mosi_bit = 7; - /* Bits for slave->master direction */ - rayer_miso_bit = 6; - break; - case TYPE_XILINX_DLC5: - msg_pdbg("Using Xilinx Parallel Cable III (DLC 5) pinout.\n"); - /* Bits for master->slave direction */ - rayer_cs_bit = 2; - rayer_sck_bit = 1; - rayer_mosi_bit = 0; - /* Bits for slave->master direction */ - rayer_miso_bit = 4; - } + msg_pinfo("Using %s pinout.\n", prog->description); + pinout = (struct rayer_pinout *) prog->private; if (rget_io_perms()) return 1; @@ -175,6 +186,11 @@ int rayer_spi_init(void) /* Get the initial value before writing to any line. */ lpt_outbyte = INB(lpt_iobase); + if (pinout->shutdown) + register_shutdown(pinout->shutdown, (void*)pinout); + if (pinout->preinit) + pinout->preinit(pinout); + if (bitbang_spi_init(&bitbang_spi_master_rayer)) return 1; -- 1.8.1.1

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Re: [flashrom] MX25U1635E (on OLPC XO-4 B1) with flashrom r1657
by Stefan Tauner 25 Aug '13

25 Aug '13

On Tue, 19 Mar 2013 16:12:43 +1100 James Cameron <quozl(a)laptop.org> wrote: > G'day, > > I'm an Open Firmware developer working for One Laptop per Child. > > We have used the MX25U3235E chip in revision B1 of our XO-4 design, > and I am trying to use flashrom (r1657) with a Bus Pirate to read from > a chip. > > I see you pushed a patch for this chip in the past few days. A happy > coincidence perhaps. > > Is there anything I can do to help you change TEST_UNTESTED to > something else? > > (Sorry if this is an obvious question, but I have very little > knowledge of flashrom, having used for the first time yesterday with a > different chip. Mostly we program the chip from within Open > Firmware.) > > I changed TEST_UNTESTED to TEST_OK_PR on my system, and captured the > attached logs. > > While the identify worked, the read gave errors, and the output file > contained 0xff only. We have never intentionally enabled any block > protection on this chip. > Hello James, the .tested field is only used for QA and telling the user about it. Changing it does not influence functionality. If you are in a hurry skip this paragraph. :) I am a bit puzzled at the moment regarding the (read) log. If you look at the detailed output of the contents of the status register at line 132 ff. you see that flashrom (mistakenly) reads 0xFF, which leads to the assumption that a block protection is enabled (see bottom of page 26 in the datasheet of the chip; that's quite a standard layout of a SPI flash status register...). It then tries to disable the "protection" and fails because another bit in the status register - the WIP bit - remains at 1. I have no idea why it (always) reads 0xFF from the status register... I have checked the opcode and it is correct, and there is nothing fancy about... apart from one thing I just noticed which you could test: in spi_read_status_register() in spi25_statusreg.c replace 2 with 1 in the array declaration readarr[2] so that this line becomes unsigned char readarr[1]; /* JEDEC_RDSR_INSIZE=1 but wbsio needs 2 */ wbsio is our driver for a very annoying winbond SPI master and as the fixme in the function says, this hack should not be in the generic code. If the macronix chip does not repeat the status register contents when one reads more than one byte after sending the RDSR (read status register) opcode (which chips usually do) but 0xFF then we have found the culprit. PS: please send further mails to flashrom(a)flashrom.org - our mailing list, thanks. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

2 2

[PATCH] Add git support to the Makefile
by Carl-Daniel Hailfinger 21 Aug '13

21 Aug '13

flashrom relies on svn to export tarballs and only prints the last svn revision in the version message even if flashrom is in a git tree. Print extended version information (version, svn revision, git hash, repository URL). Allow exporting from git trees. This should make git users first-class citizens like svn users. Side note: If anyone has an idea how to make the export target more beautiful (80 column limit etc.), please tell me. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-gitfriendly/Makefile =================================================================== --- flashrom-gitfriendly/Makefile (Revision 1145) +++ flashrom-gitfriendly/Makefile (Arbeitskopie) @@ -97,13 +97,15 @@ # of the checked out flashrom files. # Note to packagers: Any tree exported with "make export" or "make tarball" # will not require subversion. The downloadable snapshots are already exported. -SVNVERSION := $(shell LC_ALL=C svnversion -cn . 2>/dev/null | sed -e "s/.*://" -e "s/$[0-9]*$.*/\1/" | grep "[0-9]" || LC_ALL=C svn info . 2>/dev/null | awk '/^Revision:/ {print $$2 }' | grep "[0-9]" || LC_ALL=C git svn info . 2>/dev/null | awk '/^Revision:/ {print $$2 }' | grep "[0-9]" || echo unknown) +SCMVERSION := $(shell LC_ALL=C svnversion -cn . 2>/dev/null | sed -e "s/.*://" -e "s/$[0-9]*$.*/\1/" | grep "[0-9]" || LC_ALL=C svn info . 2>/dev/null | awk '/^Revision:/ {print $$2 }' | grep "[0-9]" || LC_ALL=C git svn info . 2>/dev/null | awk '/^Revision:/ {print $$2 }' | grep "[0-9]" || echo unknown) +SCMEXTVERSION := $(shell LC_ALL=C git rev-parse HEAD 2>/dev/null | sed 's/^./-\0/') +SCMURL := $(shell LC_ALL=C svn info 2>/dev/null | grep URL: | sed 's/.*URL:[[:blank:]]*//' | grep ^. || LC_ALL=C git remote show origin 2>/dev/null |grep URL: | sed 's/.*URL:[[:blank:]]*//' | grep ^. || echo unknown ) RELEASE := 0.9.2 -VERSION := $(RELEASE)-r$(SVNVERSION) +VERSION := $(RELEASE)-r$(SCMVERSION)$(SCMEXTVERSION) RELEASENAME ?= $(VERSION) -SVNDEF := -D'FLASHROM_VERSION="$(VERSION)"' +SCMDEF := -D'FLASHROM_VERSION="$(VERSION)"' -D'FLASHROM_SCMURL="$(SCMURL)"' # Always enable internal/onboard support for now. CONFIG_INTERNAL ?= yes @@ -310,7 +312,7 @@ TAROPTIONS = $(shell LC_ALL=C tar --version|grep -q GNU && echo "--owner=root --group=root") %.o: %.c .features - $(CC) -MMD $(CFLAGS) $(CPPFLAGS) $(FEATURE_CFLAGS) $(SVNDEF) -o $@ -c $< + $(CC) -MMD $(CFLAGS) $(CPPFLAGS) $(FEATURE_CFLAGS) $(SCMDEF) -o $@ -c $< # Make sure to add all names of generated binaries here. # This includes all frontends and libflashrom. @@ -420,9 +422,12 @@ export: @rm -rf $(EXPORTDIR)/flashrom-$(RELEASENAME) - @svn export -r BASE . $(EXPORTDIR)/flashrom-$(RELEASENAME) - @sed "s/^SVNVERSION.*/SVNVERSION := $(SVNVERSION)/" Makefile >$(EXPORTDIR)/flashrom-$(RELEASENAME)/Makefile - @LC_ALL=C svn log >$(EXPORTDIR)/flashrom-$(RELEASENAME)/ChangeLog + @svn export -r BASE . $(EXPORTDIR)/flashrom-$(RELEASENAME) 2>/dev/null || git checkout-index -a -f --prefix=$(EXPORTDIR)/flashrom-$(RELEASENAME)/ + @# If SCMVERSION or SCMEXTVERSION contain a slash or SCMURL contains a hash, this will explode + @sed "s/^SCMVERSION.*/SCMVERSION := $(SCMVERSION)/;s/^SCMEXTVERSION.*/SCMEXTVERSION := $(SCMEXTVERSION)/;s#^SCMURL.*#SCMURL := $(SCMURL)#" Makefile >$(EXPORTDIR)/flashrom-$(RELEASENAME)/Makefile + @# ChangeLog should be in English, but we want UTF-8 for names. + @( LC_ALL=en_US.UTF-8 svn log 2>/dev/null || LC_ALL=en_US.UTF-8 git log 2>/dev/null || echo "Unable to extract log from SCM" ) >$(EXPORTDIR)/flashrom-$(RELEASENAME)/ChangeLog + @rm -f $(EXPORTDIR)/flashrom-$(RELEASENAME)/.gitignore $(EXPORTDIR)/flashrom-$(RELEASENAME)/.gitattributes $(EXPORTDIR)/flashrom-$(RELEASENAME)/.gitmodules @echo Exported $(EXPORTDIR)/flashrom-$(RELEASENAME)/ tarball: export Index: flashrom-gitfriendly/flashrom.c =================================================================== --- flashrom-gitfriendly/flashrom.c (Revision 1145) +++ flashrom-gitfriendly/flashrom.c (Arbeitskopie) @@ -1355,6 +1355,7 @@ void print_version(void) { msg_ginfo("flashrom v%s", flashrom_version); + msg_ginfo(" from " FLASHROM_SCMURL ","); print_sysinfo(); } @@ -1362,7 +1363,6 @@ { msg_ginfo("flashrom is free software, get the source code at " "http://www.flashrom.org\n"); - msg_ginfo("\n"); } int selfcheck(void) -- http://www.hailfinger.org/

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Re: [flashrom] [coreboot] Dualbios on GA-MA770-UD3
by Carl-Daniel Hailfinger 10 Aug '13

10 Aug '13

Hi Vadim, thanks for your mail. I have added the flashrom mailing list in CC: because we should develop a generic way to handle DualBIOS and similar techniques. On 09.04.2010 08:12, Vadim Girlin wrote: > I'm going to try coreboot on Gigabyte GA-MA770-UD3. > It's AMD 770 (RX780 / SB700). > > My motherboard supports hardware dual bios - with two chips on it. > I'm going to try flashing backup chip and boot from it. It seems to be > possible - I've tested it (flashing at least). Chips on this board could > be switched by changing bit 0 at undocumented register EF on LDN 7 of > IT8720. I can use slightly patched flashrom for accessing any chip I > want without any problems. And this is tested many times. > > My idea is to use backup chip for debugging - that always keeps my > chance to reboot from main bios chip. And removes the need for > desoldering etc. > > And second problem is that original bios is checking second chip - and > trying to recover it by flashing the bios from main chip on reboot? > rewriting coreboot. AFAICS this could be solved by including some > signatures etc. It seems to be easy to find out. May be someone is > working on this? > > BTW I can send the patch for flashrom - but I think that with > information I mentioned above somebody could make it much better than my > ugly hack. I hope the regs should be the same for all latest Gigabyte > MBs using IT8720/18 > It would be great if you could send that patch. It will help us make a flashrom design decision that works for all boards with multiple flash chips. By the way, some of us have good contacts at ITE, so we can ask ITE for details about the undocumented registers. Regards, Carl-Daniel -- http://www.hailfinger.org/

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Re: [flashrom] Invalid OPCODE 0x9f
by Stefan Tauner 07 Aug '13

07 Aug '13

The restricted opcode is not so unusual. We have encountered the same with some thinkpads. Vendors don't need proper RDID because they usually know which chip is installed so they don't have to support 300+ chips like flashrom does. On Mon, 29 Apr 2013 14:47:35 +0400 Vasiliy Vylegzhanin <6vasia(a)gmail.com> wrote: > 0x54: 0x00000000 FREG0: Flash Descriptor region (0x00000000-0x00000fff) is read-write. > 0x58: 0x07ff0580 FREG1: BIOS region (0x00580000-0x007fffff) is read-write. > 0x5C: 0x057f0003 FREG2: Management Engine region (0x00003000-0x0057ffff) is read-write. > 0x60: 0x00020001 FREG3: Gigabit Ethernet region (0x00001000-0x00002fff) is read-write. > 0x64: 0x00000fff FREG4: Platform Data region is unused. > 0x74: 0x00000000 (PR0 is unused) > 0x78: 0x00000000 (PR1 is unused) > 0x7C: 0x00000000 (PR2 is unused) > 0x80: 0x87ff0770 PR3: WARNING: 0x00770000-0x007fffff is read-only. > 0x84: 0x875f0580 PR4: WARNING: 0x00580000-0x0075ffff is read-only. The protected regions are a bigger problem. This configuration protects almost the complete BIOS region and this can not be disabled at runtime. Does the vendor offer updates for the BIOS? Did you look into the BIOS configuration menu if there is a switch to allow BIOS modifications? -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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[RFC] Layout handling...
by Carl-Daniel Hailfinger 12 Jul '13

12 Jul '13

Hi, before we change flashrom to work with current layout requirements, we should summarize the features we need/want, and then decide how to handle the individual layout regions internally. Terms: "write strategy" describes a combination of erase+write commands with a given block size, touching some blocks. "read protected" describes a region which can not be read. "write protected" describes a region which can not be written. "write once" describes a region which can be written exactly once in the chip lifetime. If you add a feature to the list, please give it a nickname so we know which feature people are referring to. Some of the features below might not be desirable, but I want to list them anyway so we can explicitly declare them as unsupported if needed. fullwrite-unrestricted: Write a chip-sized image, no special read/write restrictions of the chip, no layout file needs to be specified. Default write case right now. fullwrite-noread: Write a chip-sized image, reading anything from the chip is not possible. Many DVD writers fall in that category. No verification, violates our reliability guarantees. fullwrite-postread: Write a chip-sized image, reading anything from the chip is only possible after write. Chips which are read-locked until a full erase/write fall in that category. Do those exist as standalone flash chips or only integrated into processors? fullwrite-partialread: Write a chip-sized image, reading is only possible in some chip regions. Only partial verification, violates our reliability guarantees. fullwrite-partialwrite: Write a chip-sized image, but writing is only possible in some regions. This is obviously a conflict unless the image has the same contents as the chip in the write-protected regions and there is a possible write strategy for the whole image which does not touch the write-protected regions. Should flashrom always refuse this scenario, or only refuse it in case of conflicts? partialwrite-unrestricted: Write only parts of an image, the rest of the chip contents is kept, no special read/write restrictions. partialwrite-partialread: Write only parts of an image, the rest of the chip contents is kept, reading is only possible in some chip regions. If no read-protected regions are written and a suitable write strategy exists, should flashrom warn? If a read-protected region is written, should flashrom warn/refuse due to reliability requirements? partialwrite-partialwrite: Write only parts of an image, the rest of the chip contents is kept, writing is only possible in some chip regions. If no write-protected regions are written and a suitable write strategy exists, should flashrom warn? flashrom will refuse to write a write-protected region. fullread-unrestricted: Read the full chip, no special read restrictions of the chip. partialread-unrestricted: Read only parts of a chip, no special read restrictions of the chip. partialread-partialread: Read only parts of a chip, some regions are read-protected. flashrom should refuse to read any read-protected regions. partialread-imagefiller: If only parts of a chip are read and the read image has full chip size, what should be used as filler for unread regions? 0x00 or 0xff? partialread-layout-imagesize: If only parts of a chip are read, should the read image still have full chip size with all read regions filled in at the respective locations? partialread-layout-split: If only parts of a chip are read, should it be possible to write each region (or a combination thereof) to a separate image file, and would that mapping be specified in the layout file? partialwrite-layout-split: If only parts of a chip are written, should it be possible to collect each part of the new image from a separate image file, and would that mapping be specified in the layout file? readwrite-protection-time: Which read protection and write protection times exist? Temporary lock until unlock, temporary lock until chip soft reset, temporary lock until chip/programmer hard reset (powerdown or reset line), permanent eternal lock. readwrite-protection-type: Which read protection and write protection types exist? Programmer lock (e.g. Intel SPI), hardware chip lock (WP pin), software chip lock (chip command). readwrite-protection-interaction: How should we express this situation: A region is write-locked with a software chip lock, but to remove that software chip lock, a hardware chip lock has to be disabled first, then the software chip lock can be disabled. partialaccess-crash: Some regions in the chip are really off-limits and will cause an unrecoverable error (system crash) when accessed (read or write). That seems to be the case for some EC/flash interactions. Comments? Any forks of flashrom (e.g. chromium) which need infrastructure features not mentioned above? Regards, Carl-Daniel -- http://www.hailfinger.org/

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Re: [flashrom] AMD - SP5100 - take SPI ownership (1/2)
by Rudolf Marek 20 Jun '13

20 Jun '13

Hi All > Using flashrom (with IMC patch), flash coreboot base build for AMD Persimmon > board. > Passes verifying flash; but IMC resume failed. > Poweroff - doesn't fully power off. Stops with "Power down."; manual poweroff I guess because coreboot does not provide any IMC firmware here. > > --- > > Reboot system, and able to ssh into system; no VGA from the board itself. > No VGA is expected because I did not add a vBios to the coreboot image. > > --- > > Trying to flash back the AMI original bios; fails with: > > root@debian:~# ./flashrom_imcpatch -p internal -w AMI.rom > flashrom v0.9.6.1-r1564 on Linux 2.6.32-5-686 (i686) > flashrom is free software, get the source code at http://www.flashrom.org > > Calibrating delay loop... OK. > coreboot table found at 0xc717d000. > Found chipset "AMD SB7x0/SB8x0/SB9x0". Enabling flash write... (Shutting down IMC failed!) > FAILED! > FATAL ERROR! > Error: Programmer initialization failed. Here I guess the bit which is telling that IMC is active survived reboot. > --- > > Power off, unplug board power supply, moving both jumpers (JP12, JP13 on pin 2-3) for 30 seconds to clear CMOS settings. > Reboot; Retry flashrom AMI; outputs: > > root@debian:~# ./flashrom_imcpatch -p internal -w AMI.rom > flashrom v0.9.6.1-r1564 on Linux 2.6.32-5-686 (i686) > flashrom is free software, get the source code at http://www.flashrom.org > > Calibrating delay loop... OK. > coreboot table found at 0xc717d000. > Found chipset "AMD SB7x0/SB8x0/SB9x0". Enabling flash write... OK. This confirms that IMC is "dead" here, there is no MBOX interface no bit which tells if IMC is active. > Found SST flash chip "SST25VF032B" (4096 kB, SPI) at physical address 0xffc00000 . > Flash image seems to be a legacy BIOS. Disabling coreboot-related checks. > Reading old flash chip contents... done. > Erasing and writing flash chip... ERASE FAILED at 0x00000000! Expected=0xff, Read=0x7f, failed byte count from 0x00000000-0x00000fff: 0x200 > ERASE FAILED! > Reading current flash chip contents... done. ERASE FAILED at 0x00000008! Expected=0xff, Read=0x7f, failed byte count from 0x00000000-0x00007fff: 0xfff > ERASE FAILED! > Reading current flash chip contents... done. ERASE FAILED at 0x00000008! Expected=0xff, Read=0x7f, failed byte count from 0x00000000-0x0000ffff: 0x1fff > ERASE FAILED! > Reading current flash chip contents... done. ERASE FAILED at 0x00000008! Expected=0xff, Read=0x7f, failed byte count from 0x00000000-0x003fffff: 0x7ffff > ERASE FAILED! > Reading current flash chip contents... done. ERASE FAILED at 0x00000000! Expected=0xff, Read=0x7f, failed byte count from 0x00000000-0x003fffff: 0x80000 > ERASE FAILED! I admit this is strange. The only explanation is that the IMC tries to run non-existing stuff. So it in fact tries to execute something and there is no way it could tell us that it is active. Not sure what to do here. I know there is some soft strap override but I dont know if current strap can be read to detect if IMC is enabled but actually not doing anything. Maybe this is getChipSysMode() in CIMX. > Power on > Nothing > Yes because it erased most of the flash ;) So... This is going to be complicated. Can you please send me in private both images? Or paste URL where i can get ami bios image. I will check if IMC firmware is there or not (I guess none in coreboot). What we could possibly do is to re-add a firmware to coreboot image. But we would have to override the straps and activate the imc. There is also BuildParameters.ImcEnableOverWrite in SB800 CIMX. What is your goal here anyway? To have smooth transition to coreboot? Or you just reported this issue? I guess we need to implement some safety checks that if IMC strap is always enabled then IMC firmware must exist and ideally be same as in flash. But first we need to know what CIMX is doing. if 1) EC is disabled and it is re-enabled by soft strap This seems not to be the case, because if (validateImcFirmware (pConfig)) { softwareToggleImcStrapping (pConfig); It will enable the IMC only if valid firmware is found. And for CIMX800 we are not doing this, only hudson has AMD firmware. 2) if it is enabled by some hardware strap This could be detected most likely by getChipSysMode() in this case we need to disallow write of firmware which has no IMC code. Here are couple of problems, what to do if firmware is there, but different for example... Or with coreboot may happen it is on different location. Franly I don't know how to deal with that because for this I would need detailed knowledge of the firmware itself. I only disassembled that and I can see it just spins in memory when 0xb4 is invoked and waits for 0xb5 (and I have seen sometimes for 0xb6) And this gets worse because Hudson has USB firmware and Gigabit ethernet firmware. Which are are same PITA. Thanks Rudolf > --- > > Cheers, > Michel. > > > -----Original Message----- > From: Rudolf Marek [mailto:r.marek@assembler.cz] > Sent: Saturday, March 30, 2013 3:54 AM > To: Racine, Michel > Cc: Stefan Tauner; roxfan; frederic.temporelli(a)bull.net; wmkamp(a)datakamp.de; flashrom(a)flashrom.org > Subject: Re: [flashrom] AMD - SP5100 - take SPI ownership (1/2) > > Hi, > > Found chipset "AMD SB7x0/SB8x0/SB9x0" with PCI ID 1002:439d. Enabling flash write... > EC SIO is at 0x16e > EC MBOX is at 0x3e > (Shutting down IMC) > SPI base address is at 0xfec10000 > > This means that firmware correctly responded to the command and most likely moved itself to internal RAM. > > Verifying flash... VERIFIED. > > EC SIO is at 0x16e > EC MBOX is at 0x3e > (IMC resume failed!) > > This means that firmware was not able to continue at the end? > > I have a couple of questions: > > 1) did you perform full power cycle (even unplugging the PSU)? > > I suspect that the IMC may run even if main cpu is off. I also suspect it fully initializes only if performing this "cold boot". > > 2) what was the update? It was from original BIOS to coreboot? Does coreboot have a embedded IMC image? Does the IMC image start at the same location? > > What we could additionally check is if the IMC firmware location does not match in source and dest image, bail out. Or if the base addr has been changed. > > Thanks > Rudolf >

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Re: [flashrom] [PATCH 0/2] AMD sbxxx hacks.
by Stefan Tauner 16 Jun '13

16 Jun '13

On Thu, 18 Apr 2013 18:02:37 +0200 Stefan Tauner <stefan.tauner(a)student.tuwien.ac.at> wrote: > andor had some problems with how coreboot configured the SPI controller. > let's see if this hack fixes that. while the patches are wrong... (fastReadEnable is a single bit), they apparently improve the situation on boards where the spi controller is not configured correctly. -- Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [flashrom] USB 3 PCI Card support (request to add device)
by Philipp Post 13 Jun '13

13 Jun '13

I have added some flashrom and linux logs which might be helpfull: The USB 3 PCI card has the following system properties: DRIVER=xhci_hcd PCI_CLASS=C0330 PCI_ID=1033:0194 PCI_SUBSYS_ID=1033:0194 PCI_SLOT_NAME=0000:03:00.0 MODALIAS=pci:v00001033d00000194sv00001033sd00000194bc0Csc03i30 There is also a PCI NIC Intel 82541PI Gigabit Ethernet Controller (8086:107c, BDF 02:0a.0) and a PCI soundcard installed. Tried to read the flash rom out of the 82541PI Intel NIC without problems. /sys/bus/pci/devices/0000:02:0a.0 of the Intel NIC also gives access to "rom" which the USB 3 and the soundcard do not. I am not sure if that means that the rom is not accessible at all or if Ubuntu just does not know how. Thanks in advance, brgds Philipp -----Ursprüngliche Nachricht----- Von: Philipp Post [mailto:Post.Philipp@googlemail.com] Gesendet: Donnerstag, 24. Januar 2013 19:23 An: 'flashrom(a)flashrom.org' Betreff: USB 3 PCI Card support (request to add device) Good day, following configuration: - USB 3 PCI (not PCI-Express) card with RENESAS uPD720200A(Revision 4) USB chip and ATMEL AT25F512B (ATMEL 1138, 25F512B, SSH) rom chip in - IBM NetVista 8305 Desktop PC - built year 2003 The issue with the card is that it needs a flash rom update to work with Windows Vista and up, otherwise the device does not work at all in these OS ("device cannot start"). Windows XP with Renesas drivers and Linux Ubuntu 11.3 out of the box works fine. RENESAS has a rom update for the chip and a flash update tool which however does not work with PCI cards, but just chips soldered to mainboards. At least this seems to me the reason why it does not work. Chip is recognized but the RENESAS tool says "Can not load / access firmware". The tool has the option to change the device / vendor id as well via .ini file. The card used is the only PCI USB 3 card on the market and basically works very well when it works - with max PCI speed of course, which means approx. double speed of USB 2. The card exists in hardware version 1 (RENESAS chip uPD720200A) and 2 (RENESAS chip uPD720202). I do just have access to hardware version 1. The name of the manufacturer behind the card is unknown to me, but it could be an ADDONICS product. I do not have a technical drawing of the card and I fear I can not obtain one but I do have the card itself. My question: would it be possible to incorporate this card into flashrom? Would be great if someone could do it as I do not have the necessary skills to do it myself. In case you need further information, please let me know. Thanks in advance, brgds Philipp Links and further reading: -------------------------- Card Information from different sellers (same card): http://www.addonics.com/products/ad2u3pci.php http://eu.startech.com/Cards-Adapters/USB-3.0/Cards/2-Port-PCI-SuperSpeed-US B-3-Card-Adapter~PCIUSB3S2 http://www.lindy.de/premium-usb-3-karte-2-port-pci/51082.html ATMEL rom specification (contains info how to write rom images): www.atmel.com/Images/doc3689.pdf Renesas USB chip information: http://www.renesas.eu/products/soc/usb_assp/product/upd720200a/index.jsp RENESAS rom update 4.0.2.0 with Windows updater (32 + 64 Bit) and drivers: http://www.station-drivers.com/page/renesas.htm We need: "Firmware Version 4.0.2.0 pour uPD720200a" RENESAS MS DOS flash update tool (which did not do the job): http://www.computerbase.de/forum/attachment.php?attachmentid=283282&d=133832 3319 IBM NetVista 8305 Hardware Maintenance Manual: http://download.lenovo.com/ibmdl/pub/pc/pccbbs/netvista_pdf/24p2969.pdf Hardware Ids: Renesas Electronics USB 3.0 Host Controller: PCI\VEN_1033&DEV_0194&SUBSYS_01941033&REV_04\5&25043F3&0&0048F0 Renesas Electronics USB 3.0 Root Hub NUSB3\ROOT_HUB30\6&2D374EF3&2

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flashrom May 2013