flashrom June 2010

flashrom@flashrom.org

74 participants
219 discussions

[PATCH] Add a udev rules file for flashrom
by Uwe Hermann 27 Jul '10

27 Jul '10

See patch. Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org

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AMD CS5536 now detected twice with r1057
by Guenter 26 Jul '10

26 Jul '10

Hi, board is PC-Engines Alix 2C3: http://www.pcengines.ch/alix2c3.htm while r1001 detects the AMD CS5536 correctly only once: flashrom v0.9.2-r1001 on Linux 2.6.32-1 (i586), built with libpci 3.1.7, GCC 4.4.3 flashrom is free software, get the source code at http://www.flashrom.org No coreboot table found. Found chipset "AMD CS5536", enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Calibrating delay loop... OK. Found chip "AMIC A49LF040A" (512 KB, LPC) at physical address 0xfff80000. === This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -Vr, -Vw, -VE), and mention which mainboard or programmer you tested. Thanks for your help! === No operations were specified. now recent r1057 gives a warning that AMD CS5536 is detected twice: flashrom v0.9.2-r1057 on Linux 2.6.32-1 (i586), built with libpci 3.1.7, GCC 4.4.3, little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OK. No coreboot table found. Found chipset "AMD CS5536", enabling flash write... OK. WARNING: unexpected second chipset match: "AMD CS5536" ignoring, please report lspci and board URL to flashrom(a)flashrom.org! This chipset supports the following protocols: Non-SPI. Found chip "AMIC A49LF040A" (512 KB, LPC) at physical address 0xfff80000. No operations were specified. lspci -nn 00:01.0 Host bridge [0600]: Advanced Micro Devices [AMD] CS5536 [Geode companion] Host Bridge [1022:2080] (rev 33) 00:01.2 Entertainment encryption device [1010]: Advanced Micro Devices [AMD] Geode LX AES Security Block [1022:2082] 00:09.0 Ethernet controller [0200]: VIA Technologies, Inc. VT6105M [Rhine-III] [1106:3053] (rev 96) 00:0a.0 Ethernet controller [0200]: VIA Technologies, Inc. VT6105M [Rhine-III] [1106:3053] (rev 96) 00:0b.0 Ethernet controller [0200]: VIA Technologies, Inc. VT6105M [Rhine-III] [1106:3053] (rev 96) 00:0f.0 ISA bridge [0601]: Advanced Micro Devices [AMD] CS5536 [Geode companion] ISA [1022:2090] (rev 03) 00:0f.2 IDE interface [0101]: Advanced Micro Devices [AMD] CS5536 [Geode companion] IDE [1022:209a] (rev 01) 00:0f.4 USB Controller [0c03]: Advanced Micro Devices [AMD] CS5536 [Geode companion] OHC [1022:2094] (rev 02) 00:0f.5 USB Controller [0c03]: Advanced Micro Devices [AMD] CS5536 [Geode companion] EHC [1022:2095] (rev 02) Günter.

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Re: [flashrom] [PATCH] Board enable for ASUS P4SD-LA (HP OEM)
by Carl-Daniel Hailfinger 24 Jul '10

24 Jul '10

Hi csh tmp, I didn't see a response from you for Michael's patch for your P4SD-LA (HP OEM) board. On 24.04.2010 11:13, Michael Karcher wrote: > This one was so easy that I didn't wait for a request. > > Signed-off-by: Michael Karcher <flashrom(a)mkarcher.dialup.fu-berlin.de> > The patch is available at http://patchwork.coreboot.org/patch/1261/ Download link for the patch: http://patchwork.coreboot.org/patch/1261/raw/ Can you please test and tell us if it works? Regards, Carl-Daniel -- http://www.hailfinger.org/

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[RFC] National Semiconductor DP83815 NIC patch
by Andrew Morgan 21 Jul '10

21 Jul '10

Hi, I have a couple of Netgear FA311 network cards, which have DP83815DVNG chips on board, and a space to mount a 32-pin boot ROM socket. Looking at the datasheet for the chip I have created this patch. The datasheet suggests that reads and writes must be done 32 bits at a time, and only at 32 bit offsets. This seems strange for chips which have an 8 bit data bus. I don't think this code is ready for inclusion in flashrom yet, but if anyone has a card with this chip and can test it out then give it a go. I'm pretty sure it won't just work though. It might even destroy your computer/house/planet. I can't test it yet because the cards don't have a 32pin socket mounted on them. If and when I can add one then I can do some tests. This is my first 'large' patch so let me know what I have got wrong. :) Signed-off-by: Andrew Morgan <ziltro(a)ziltro.com> -- Andrew.

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[PATCH] Add SST25VF064C SPI flash
by Ed Swierk 21 Jul '10

21 Jul '10

Add definition for the SST25VF064C SPI flash chip. Signed-off-by: Ed Swierk <eswierk(a)aristanetworks.com> --- Index: flashrom-0.9.2-r1057/flashchips.c =================================================================== --- flashrom-0.9.2-r1057.orig/flashchips.c +++ flashrom-0.9.2-r1057/flashchips.c @@ -3871,6 +3871,40 @@ struct flashchip flashchips[] = { { .vendor = "SST", + .name = "SST25VF064C", + .bustype = CHIP_BUSTYPE_SPI, + .manufacture_id = SST_ID, + .model_id = SST_25VF064C, + .total_size = 8192, + .page_size = 256, + .tested = TEST_OK_PREW, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 2048} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 256} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 128} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {8 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + }, + }, + .write = spi_chip_write_1, + .read = spi_chip_read, + }, + + { + .vendor = "SST", .name = "SST25VF040.REMS", .bustype = CHIP_BUSTYPE_SPI, .manufacture_id = SST_ID, Index: flashrom-0.9.2-r1057/flashchips.h =================================================================== --- flashrom-0.9.2-r1057.orig/flashchips.h +++ flashrom-0.9.2-r1057/flashchips.h @@ -399,6 +399,7 @@ #define SST_25VF016B 0x2541 #define SST_25VF032B 0x254A #define SST_25VF032B_REMS 0x4A /* REMS or RES opcode */ +#define SST_25VF064C 0x254B #define SST_26VF016 0x2601 #define SST_26VF032 0x2602 #define SST_27SF512 0xA4

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Re: [flashrom] [PATCH] Add support for RayeR SPIPGM hardware.
by Carl-Daniel Hailfinger 21 Jul '10

21 Jul '10

Hi, On 02.06.2010 09:47, RayeR wrote: > Carl-Daniel Hailfinger wrote: >> On 01.06.2010 11:54, rayer wrote: >>> it still hangs while autodetecting flash chip at AE49F2008 (is >>> displayed as last probed), >>> only with -c option it works. >>> >> Does it really work with -c CHIPNAME or do you need -f as well? >> > Yes, no -f needed. > Btw still problem with calibrating delay loop. The delay loop problem is now fixed. >> I found a bug in the bitbanging SPI core (buffer confusion) and fixed >> it. >> This version also reduces reach chunk size to 256 bytes instead of 65536 >> bytes. That makes buffer management more efficient (only one round of >> memory allocations). >> > I did't tested lpt-spi yet, I'll have to prepare some flash chip first... It would be cool if you could test the lpt-spi code. New flashrom.exe is available at http://khepri.openbios.org/~idwer/flashrom/r1039-patchwork-1441/ flashrom -p rayer_bitbang_spi -V Regards, Carl-Daniel -- http://www.hailfinger.org/

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[PATCH] drkaiser: MEM BAR fixes
by Carl-Daniel Hailfinger 17 Jul '10

17 Jul '10

Use the BAR value returned by pcidev_init which automatically uses the correct BAR mask. Truncate flash chip addresses to fit into the 128 kB memory window. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-drkaiser_pcibar_mask_mem_bounds_checking/drkaiser.c =================================================================== --- flashrom-drkaiser_pcibar_mask_mem_bounds_checking/drkaiser.c (Revision 946) +++ flashrom-drkaiser_pcibar_mask_mem_bounds_checking/drkaiser.c (Arbeitskopie) @@ -40,16 +40,13 @@ uint32_t addr; get_io_perms(); - pcidev_init(PCI_VENDOR_ID_DRKAISER, PCI_BASE_ADDRESS_2, - drkaiser_pcidev, programmer_param); + addr = pcidev_init(PCI_VENDOR_ID_DRKAISER, PCI_BASE_ADDRESS_2, + drkaiser_pcidev, programmer_param); /* Write magic register to enable flash write. */ pci_write_word(pcidev_dev, PCI_MAGIC_DRKAISER_ADDR, PCI_MAGIC_DRKAISER_VALUE); - /* TODO: Mask lower bits? How many? 3? 7? */ - addr = pci_read_long(pcidev_dev, PCI_BASE_ADDRESS_2) & ~0x03; - /* Map 128KB flash memory window. */ drkaiser_bar = physmap("Dr. Kaiser PC-Waechter flash memory", addr, 128 * 1024); @@ -70,10 +67,12 @@ void drkaiser_chip_writeb(uint8_t val, chipaddr addr) { - mmio_writeb(val, drkaiser_bar + addr); + /* Restrict flash accesses to the 128kB memory window. */ + mmio_writeb(val, drkaiser_bar + (addr & ((1 << 17) - 1))); } uint8_t drkaiser_chip_readb(const chipaddr addr) { - return mmio_readb(drkaiser_bar + addr); + /* Restrict flash accesses to the 128kB memory window. */ + return mmio_readb(drkaiser_bar + (addr & ((1 << 17) - 1))); } -- "I do consider assignment statements and pointer variables to be among computer science's most valuable treasures." -- Donald E. Knuth

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[PATCH] Refactor/fix read-to-file
by Carl-Daniel Hailfinger 13 Jul '10

13 Jul '10

Print an error message on read errors and abort instead of proceeding anyway. Improve error checking in file write, chip read and chip verify. Refactor the read routines a bit to split reading from file writing. Parts of this patch were already present in [PATCH] Avoid scary warning if nothing changed Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-read_error_checking/flash.h =================================================================== --- flashrom-read_error_checking/flash.h (Revision 1063) +++ flashrom-read_error_checking/flash.h (Arbeitskopie) @@ -578,7 +578,7 @@ int read_memmapped(struct flashchip *flash, uint8_t *buf, int start, int len); int erase_flash(struct flashchip *flash); struct flashchip *probe_flash(struct flashchip *first_flash, int force); -int read_flash(struct flashchip *flash, char *filename); +int read_flash_to_file(struct flashchip *flash, char *filename); void check_chip_supported(struct flashchip *flash); int check_max_decode(enum chipbustype buses, uint32_t size); int min(int a, int b); Index: flashrom-read_error_checking/cli_classic.c =================================================================== --- flashrom-read_error_checking/cli_classic.c (Revision 1063) +++ flashrom-read_error_checking/cli_classic.c (Arbeitskopie) @@ -418,7 +418,7 @@ exit(1); } printf("Please note that forced reads most likely contain garbage.\n"); - return read_flash(flashes[0], filename); + return read_flash_to_file(flashes[0], filename); } // FIXME: flash writes stay enabled! programmer_shutdown(); Index: flashrom-read_error_checking/flashrom.c =================================================================== --- flashrom-read_error_checking/flashrom.c (Revision 1063) +++ flashrom-read_error_checking/flashrom.c (Arbeitskopie) @@ -673,7 +673,12 @@ starthere = max(start, i * page_size); /* Length of bytes in the range in this page. */ lenhere = min(start + len, (i + 1) * page_size) - starthere; - flash->read(flash, readbuf, starthere, lenhere); + ret = flash->read(flash, readbuf, starthere, lenhere); + if (ret) { + msg_gerr("Verification impossible because read failed " + "at 0x%x (len 0x%x)\n", starthere, lenhere); + break; + } for (j = 0; j < lenhere; j++) { if (cmpbuf[starthere - start + j] != readbuf[j]) { /* Only print the first failure. */ @@ -1024,38 +1029,60 @@ return ret; } -int read_flash(struct flashchip *flash, char *filename) +int write_buf_to_file(unsigned char *buf, unsigned long size, char *filename) { unsigned long numbytes; FILE *image; - unsigned long size = flash->total_size * 1024; - unsigned char *buf = calloc(size, sizeof(char)); if (!filename) { - msg_gerr("Error: No filename specified.\n"); + msg_gerr("No filename specified.\n"); return 1; } if ((image = fopen(filename, "wb")) == NULL) { perror(filename); - exit(1); + return 1; } - msg_cinfo("Reading flash... "); - if (!flash->read) { - msg_cinfo("FAILED!\n"); - msg_cerr("ERROR: flashrom has no read function for this flash chip.\n"); - return 1; - } else - flash->read(flash, buf, 0, size); numbytes = fwrite(buf, 1, size, image); fclose(image); - free(buf); - msg_cinfo("%s.\n", numbytes == size ? "done" : "FAILED"); - if (numbytes != size) + if (numbytes != size) { + msg_gerr("File %s could not be written completely.\n", + filename); return 1; + } return 0; } +int read_flash_to_file(struct flashchip *flash, char *filename) +{ + unsigned long size = flash->total_size * 1024; + unsigned char *buf = calloc(size, sizeof(char)); + int ret = 0; + + msg_cinfo("Reading flash... "); + if (!buf) { + msg_gerr("Memory allocation failed!\n"); + msg_cinfo("FAILED.\n"); + return 1; + } + if (!flash->read) { + msg_cerr("No read function available for this flash chip.\n"); + ret = 1; + goto out_free; + } + if (flash->read(flash, buf, 0, size)) { + msg_cerr("Read operation failed!\n"); + ret = 1; + goto out_free; + } + + ret = write_buf_to_file(buf, flash->total_size * 1024, filename); +out_free: + free(buf); + msg_cinfo("%s.\n", ret ? "done" : "FAILED"); + return ret; +} + /* This function shares a lot of its structure with erase_flash(). * Even if an error is found, the function will keep going and check the rest. */ @@ -1383,7 +1410,7 @@ if (flash->unlock) flash->unlock(flash); - if (read_flash(flash, filename)) { + if (read_flash_to_file(flash, filename)) { programmer_shutdown(); return 1; } -- http://www.hailfinger.org/

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[PATCH] Partial writes for SPI
by Carl-Daniel Hailfinger 11 Jul '10

11 Jul '10

Every SPI programmer driver had its own completely different chip write implementation, and all of them were insufficiently commented. Create spi_write_chunked as a copy of spi_read_chunked and convert all SPI programmers to use it. No functional changes except: - Bus Pirate uses 12 Byte writes instead of 8 Byte writes - SB600 uses 5 Byte writes instead of 1 Byte writes Should work. Not for 0.9.1, but since I had that thing on my disk anyway, I figured I'd post it to the list in case someone wants to experiment with partial writes. Tests appreciated. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-partial_write_spi/spi25.c =================================================================== --- flashrom-partial_write_spi/spi25.c (Revision 982) +++ flashrom-partial_write_spi/spi25.c (Arbeitskopie) @@ -1,7 +1,7 @@ /* * This file is part of the flashrom project. * - * Copyright (C) 2007, 2008, 2009 Carl-Daniel Hailfinger + * Copyright (C) 2007, 2008, 2009, 2010 Carl-Daniel Hailfinger * Copyright (C) 2008 coresystems GmbH * * This program is free software; you can redistribute it and/or modify @@ -874,7 +874,7 @@ } /* - * Read a complete flash chip. + * Read a part of the flash chip. * Each page is read separately in chunks with a maximum size of chunksize. */ int spi_read_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize) @@ -913,6 +913,52 @@ } /* + * Write a part of the flash chip. + * Each page is written separately in chunks with a maximum size of chunksize. + */ +int spi_write_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize) +{ + int rc = 0; + int i, j, starthere, lenhere; + /* FIXME: page_size is the wrong variable. We need max_writechunk_size + * in struct flashchip to do this properly. All chips using + * spi_chip_write_256 have page_size set to max_writechunk_size, so + * we're OK for now. + */ + int page_size = flash->page_size; + int towrite; + + /* Warning: This loop has a very unusual condition and body. + * The loop needs to go through each page with at least one affected + * byte. The lowest page number is (start / page_size) since that + * division rounds down. The highest page number we want is the page + * where the last byte of the range lives. That last byte has the + * address (start + len - 1), thus the highest page number is + * (start + len - 1) / page_size. Since we want to include that last + * page as well, the loop condition uses <=. + */ + for (i = start / page_size; i <= (start + len - 1) / page_size; i++) { + /* Byte position of the first byte in the range in this page. */ + /* starthere is an offset to the base address of the chip. */ + starthere = max(start, i * page_size); + /* Length of bytes in the range in this page. */ + lenhere = min(start + len, (i + 1) * page_size) - starthere; + for (j = 0; j < lenhere; j += chunksize) { + towrite = min(chunksize, lenhere - j); + rc = spi_nbyte_program(starthere + j, buf + starthere - start + j, towrite); + if (rc) + break; + while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) + programmer_delay(10); + } + if (rc) + break; + } + + return rc; +} + +/* * Program chip using byte programming. (SLOW!) * This is for chips which can only handle one byte writes * and for chips where memory mapped programming is impossible Index: flashrom-partial_write_spi/buspirate_spi.c =================================================================== --- flashrom-partial_write_spi/buspirate_spi.c (Revision 982) +++ flashrom-partial_write_spi/buspirate_spi.c (Arbeitskopie) @@ -1,7 +1,7 @@ /* * This file is part of the flashrom project. * - * Copyright (C) 2009 Carl-Daniel Hailfinger + * Copyright (C) 2009, 2010 Carl-Daniel Hailfinger * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -319,7 +319,6 @@ int buspirate_spi_write_256(struct flashchip *flash, uint8_t *buf) { int total_size = 1024 * flash->total_size; - int i; spi_disable_blockprotect(); /* Erase first. */ @@ -330,25 +329,5 @@ } msg_pinfo("done.\n"); - /* FIXME: We could do 12 byte writes, but then we'd have to make sure - * not to cross a 256 byte page boundary. This problem only applies to - * writes, reads can cross page boundaries just fine. - */ - for (i = 0; i < total_size; i += 8) { - int l, r; - if (i + 8 <= total_size) - l = 8; - else - l = total_size - i; - - if ((r = spi_nbyte_program(i, &buf[i], l))) { - msg_perr("%s: write fail %d\n", __func__, r); - return 1; - } - - while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) - /* loop */; - } - - return 0; + return spi_write_chunked(flash, buf, 0, total_size, 12); } Index: flashrom-partial_write_spi/bitbang_spi.c =================================================================== --- flashrom-partial_write_spi/bitbang_spi.c (Revision 982) +++ flashrom-partial_write_spi/bitbang_spi.c (Arbeitskopie) @@ -1,7 +1,7 @@ /* * This file is part of the flashrom project. * - * Copyright (C) 2009 Carl-Daniel Hailfinger + * Copyright (C) 2009, 2010 Carl-Daniel Hailfinger * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -142,24 +142,7 @@ int bitbang_spi_write_256(struct flashchip *flash, uint8_t *buf) { int total_size = 1024 * flash->total_size; - int i; msg_pdbg("total_size is %d\n", total_size); - for (i = 0; i < total_size; i += 256) { - int l, r; - if (i + 256 <= total_size) - l = 256; - else - l = total_size - i; - - if ((r = spi_nbyte_program(i, &buf[i], l))) { - msg_perr("%s: write fail %d\n", __func__, r); - return 1; - } - - while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) - /* loop */; - } - - return 0; + return spi_write_chunked(flash, buf, 0, total_size, 256); } Index: flashrom-partial_write_spi/ft2232_spi.c =================================================================== --- flashrom-partial_write_spi/ft2232_spi.c (Revision 982) +++ flashrom-partial_write_spi/ft2232_spi.c (Arbeitskopie) @@ -2,7 +2,7 @@ * This file is part of the flashrom project. * * Copyright (C) 2009 Paul Fox <pgf(a)laptop.org> - * Copyright (C) 2009 Carl-Daniel Hailfinger + * Copyright (C) 2009, 2010 Carl-Daniel Hailfinger * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -288,7 +288,6 @@ int ft2232_spi_write_256(struct flashchip *flash, uint8_t *buf) { int total_size = 1024 * flash->total_size; - int i; spi_disable_blockprotect(); /* Erase first. */ @@ -299,23 +298,7 @@ } msg_pinfo("done.\n"); msg_pdbg("total_size is %d\n", total_size); - for (i = 0; i < total_size; i += 256) { - int l, r; - if (i + 256 <= total_size) - l = 256; - else - l = total_size - i; - - if ((r = spi_nbyte_program(i, &buf[i], l))) { - msg_perr("%s: write fail %d\n", __func__, r); - return 1; - } - - while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) - /* loop */; - } - - return 0; + return spi_write_chunked(flash, buf, 0, total_size, 256); } #endif Index: flashrom-partial_write_spi/sb600spi.c =================================================================== --- flashrom-partial_write_spi/sb600spi.c (Revision 982) +++ flashrom-partial_write_spi/sb600spi.c (Arbeitskopie) @@ -4,6 +4,7 @@ * Copyright (C) 2008 Wang Qingpei <Qingpei.Wang(a)amd.com> * Copyright (C) 2008 Joe Bao <Zheng.Bao(a)amd.com> * Copyright (C) 2008 Advanced Micro Devices, Inc. + * Copyright (C) 2009, 2010 Carl-Daniel Hailfinger * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -49,7 +50,6 @@ /* FIXME: SB600 can write 5 bytes per transaction. */ int sb600_spi_write_1(struct flashchip *flash, uint8_t *buf) { - int i; int total_size = flash->total_size * 1024; int result = 0; @@ -63,19 +63,7 @@ msg_pinfo("done.\n"); msg_pinfo("Programming flash"); - for (i = 0; i < total_size; i++, buf++) { - result = spi_nbyte_program(i, buf, 1); - if (result) { - msg_perr("Write error!\n"); - return result; - } - - /* wait program complete. */ - if (i % 0x8000 == 0) - msg_pspew("."); - while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP) - ; - } + result = spi_write_chunked(flash, buf, 0, total_size, 5); msg_pinfo(" done.\n"); return result; } Index: flashrom-partial_write_spi/ichspi.c =================================================================== --- flashrom-partial_write_spi/ichspi.c (Revision 982) +++ flashrom-partial_write_spi/ichspi.c (Arbeitskopie) @@ -5,7 +5,7 @@ * Copyright (C) 2008 Claus Gindhart <claus.gindhart(a)kontron.com> * Copyright (C) 2008 Dominik Geyer <dominik.geyer(a)kontron.com> * Copyright (C) 2008 coresystems GmbH <info(a)coresystems.de> - * Copyright (C) 2009 Carl-Daniel Hailfinger + * Copyright (C) 2009, 2010 Carl-Daniel Hailfinger * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -160,8 +160,6 @@ static int program_opcodes(OPCODES * op); static int run_opcode(OPCODE op, uint32_t offset, uint8_t datalength, uint8_t * data); -static int ich_spi_write_page(struct flashchip *flash, uint8_t * bytes, - int offset, int maxdata); /* for pairing opcodes with their required preop */ struct preop_opcode_pair { @@ -645,28 +643,6 @@ return -1; } -static int ich_spi_write_page(struct flashchip *flash, uint8_t * bytes, - int offset, int maxdata) -{ - int page_size = flash->page_size; - uint32_t remaining = page_size; - int towrite; - - msg_comm_debug("ich_spi_write_page: offset=%d, number=%d, buf=%p\n", - offset, page_size, bytes); - - for (; remaining > 0; remaining -= towrite) { - towrite = min(remaining, maxdata); - if (spi_nbyte_program(offset + (page_size - remaining), - &bytes[page_size - remaining], towrite)) { - printf_debug("Error writing"); - return 1; - } - } - - return 0; -} - int ich_spi_read(struct flashchip *flash, uint8_t * buf, int start, int len) { int maxdata = 64; @@ -679,12 +655,14 @@ int ich_spi_write_256(struct flashchip *flash, uint8_t * buf) { - int i, j, rc = 0; + int i, ret = 0; int total_size = flash->total_size * 1024; - int page_size = flash->page_size; int erase_size = 64 * 1024; int maxdata = 64; + if (spi_controller == SPI_CONTROLLER_VIA) + maxdata = 16; + spi_disable_blockprotect(); /* Erase first */ printf("Erasing flash before programming... "); @@ -696,19 +674,15 @@ printf("Programming page: \n"); for (i = 0; i < total_size / erase_size; i++) { - if (spi_controller == SPI_CONTROLLER_VIA) - maxdata = 16; - - for (j = 0; j < erase_size / page_size; j++) { - ich_spi_write_page(flash, - (void *)(buf + (i * erase_size) + (j * page_size)), - (i * erase_size) + (j * page_size), maxdata); - } + ret = spi_write_chunked(flash, buf + (i * erase_size), + i * erase_size, erase_size, maxdata); + if (ret) + break; } printf("\n"); - return rc; + return ret; } int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt, Index: flashrom-partial_write_spi/chipdrivers.h =================================================================== --- flashrom-partial_write_spi/chipdrivers.h (Revision 982) +++ flashrom-partial_write_spi/chipdrivers.h (Arbeitskopie) @@ -51,6 +51,7 @@ int spi_nbyte_program(int addr, uint8_t *bytes, int len); int spi_nbyte_read(int addr, uint8_t *bytes, int len); int spi_read_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize); +int spi_write_chunked(struct flashchip *flash, uint8_t *buf, int start, int len, int chunksize); int spi_aai_write(struct flashchip *flash, uint8_t *buf); /* 82802ab.c */ -- http://www.hailfinger.org/

3 8

[PATCH] Add IT8705 autodetection
by Carl-Daniel Hailfinger 10 Jul '10

10 Jul '10

I'd love to get in-depth reviews for this because it adds some sort of generic (well, ITE) Super I/O enable stage. Autodetect the ITE IT8705 Super I/O and enable flash writes if it performs LPC->Parallel translation. Remove board enables which triggered the IT8705 write enable manually. Change the IT87 SPI special case to cover IT87 LPC->SPI and LPC->Parallel translation. We need all affected board owners to test this. Probe is sufficient. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: flashrom-it8705_autodetect/flash.h =================================================================== --- flashrom-it8705_autodetect/flash.h (revision 1033) +++ flashrom-it8705_autodetect/flash.h (working copy) @@ -353,6 +353,7 @@ /* board_enable.c */ void w836xx_ext_enter(uint16_t port); void w836xx_ext_leave(uint16_t port); +int it8705f_write_enable(uint8_t port); uint8_t sio_read(uint16_t port, uint8_t reg); void sio_write(uint16_t port, uint8_t reg, uint8_t data); void sio_mask(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask); @@ -685,12 +686,11 @@ int ich_spi_send_multicommand(struct spi_command *cmds); /* it87spi.c */ -extern uint16_t it8716f_flashport; void enter_conf_mode_ite(uint16_t port); void exit_conf_mode_ite(uint16_t port); struct superio probe_superio_ite(void); +int init_superio_ite(void); int it87spi_init(void); -int it87xx_probe_spi_flash(const char *name); int it8716f_spi_send_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len); Index: flashrom-it8705_autodetect/it87spi.c =================================================================== --- flashrom-it8705_autodetect/it87spi.c (revision 1033) +++ flashrom-it8705_autodetect/it87spi.c (working copy) @@ -96,16 +96,12 @@ return ret; } -static uint16_t find_ite_spi_flash_port(uint16_t port, uint16_t id) +static uint16_t it87spi_probe(uint16_t port) { uint8_t tmp = 0; char *portpos = NULL; uint16_t flashport = 0; - switch (id) { - case 0x8716: - case 0x8718: - case 0x8720: enter_conf_mode_ite(port); /* NOLDN, reg 0x24, mask out lowest bit (suspend) */ tmp = sio_read(port, 0x24) & 0xFE; @@ -115,7 +111,8 @@ if ((programmer == PROGRAMMER_INTERNAL) && !(tmp & (0x0E))) { msg_pdbg("No IT87* serial flash segment enabled.\n"); exit_conf_mode_ite(port); - break; + /* Nothing to do. */ + return 1; } msg_pdbg("Serial flash segment 0x%08x-0x%08x %sabled\n", 0xFFFE0000, 0xFFFFFFFF, (tmp & 1 << 1) ? "en" : "dis"); @@ -159,25 +156,33 @@ } } exit_conf_mode_ite(port); - break; - /* TODO: Handle more IT87xx if they support flash translation */ - default: - msg_pdbg("SuperI/O ID %04hx is not on the controller list.\n", id); - } - return flashport; + it8716f_flashport = flashport; + if (buses_supported & CHIP_BUSTYPE_SPI) + msg_pdbg("Overriding chipset SPI with IT87 SPI.\n"); + spi_controller = SPI_CONTROLLER_IT87XX; + buses_supported |= CHIP_BUSTYPE_SPI; + return 0; } -int it87spi_common_init(void) +int init_superio_ite(void) { if (superio.vendor != SUPERIO_VENDOR_ITE) return 1; - it8716f_flashport = find_ite_spi_flash_port(superio.port, superio.model); - - if (it8716f_flashport) - spi_controller = SPI_CONTROLLER_IT87XX; - - return (!it8716f_flashport); + switch (superio.model) { + case 0x8705: + return it8705f_write_enable(superio.port); + break; + case 0x8716: + case 0x8718: + case 0x8720: + return it87spi_probe(superio.port); + break; + default: + msg_pdbg("SuperI/O ID %04hx is not on the list of flash " + "capable controllers.\n", superio.model); + } + return 1; } @@ -188,7 +193,7 @@ get_io_perms(); /* Probe for the Super I/O chip and fill global struct superio. */ probe_superio(); - ret = it87spi_common_init(); + ret = init_superio_ite(); if (!ret) { buses_supported = CHIP_BUSTYPE_SPI; } else { @@ -197,19 +202,6 @@ return ret; } -int it87xx_probe_spi_flash(const char *name) -{ - int ret; - - ret = it87spi_common_init(); - if (!ret) { - if (buses_supported & CHIP_BUSTYPE_SPI) - msg_pdbg("Overriding chipset SPI with IT87 SPI.\n"); - buses_supported |= CHIP_BUSTYPE_SPI; - } - return ret; -} - /* * The IT8716F only supports commands with length 1,2,4,5 bytes including * command byte and can not read more than 3 bytes from the device. Index: flashrom-it8705_autodetect/internal.c =================================================================== --- flashrom-it8705_autodetect/internal.c (revision 1033) +++ flashrom-it8705_autodetect/internal.c (working copy) @@ -223,8 +223,10 @@ } #if defined(__i386__) || defined(__x86_64__) - /* Probe for IT87* LPC->SPI translation unconditionally. */ - it87xx_probe_spi_flash(NULL); + /* Probe unconditionally for IT87* LPC->SPI translation and for + * IT87* Parallel write enable. + */ + init_superio_ite(); #endif board_flash_enable(lb_vendor, lb_part); Index: flashrom-it8705_autodetect/board_enable.c =================================================================== --- flashrom-it8705_autodetect/board_enable.c (revision 1033) +++ flashrom-it8705_autodetect/board_enable.c (working copy) @@ -259,33 +259,92 @@ } /** - * + * Suited for all boards with IT8705F. + * The SIS950 Super I/O probably requires the same flash write enable. */ -static int it8705f_write_enable(uint8_t port, const char *name) +int it8705f_write_enable(uint8_t port) { + uint8_t tmp; + int ret = 0; + enter_conf_mode_ite(port); - sio_mask(port, 0x24, 0x04, 0x04); /* Flash ROM I/F Writes Enable */ + tmp = sio_read(port, 0x24); + /* Check if at least one flash segment is enabled. */ + if (tmp & 0xf0) { + /* The IT8705 will respond to LPC cycles and translate them. */ + buses_supported = CHIP_BUSTYPE_PARALLEL; + /* Flash ROM I/F Writes Enable */ + tmp |= 0x04; + msg_pdbg("Enabling IT8705 flash ROM interface write.\n"); + if (tmp & 0x02) { + /* The data sheet contradicts itself about max size. */ + max_rom_decode.parallel = 1024 * 1024; + msg_pinfo("IT8705 with very unusual settings. Please " + "send the output of \"flashrom -V\" to \n" + "flashrom(a)flashrom.org to help us finish " + "support for your Super I/O. Thanks.\n"); + ret = 1; + } else if (tmp & 0x08) { + max_rom_decode.parallel = 512 * 1024; + } else { + max_rom_decode.parallel = 256 * 1024; + } + /* Safety checks. */ + if (((tmp & 0x02) && !(tmp & 0x08)) || /* 1 MB but not 512 kB */ + (!(tmp & 0x10)) || /* Not even 128 kB. */ + (!(tmp & 0x10))) { /* Not even 256/512 kB. */ + msg_perr("Inconsistent IT8705 decode size!\n"); + ret = 1; + } + if (sio_read(port, 0x25) != 0) { + msg_perr("IT8705 flash data pins disabled!\n"); + ret = 1; + } + if (sio_read(port, 0x26) != 0) { + msg_perr("IT8705 flash address pins 0-7 disabled!\n"); + ret = 1; + } + if (sio_read(port, 0x27) != 0) { + msg_perr("IT8705 flash address pins 8-15 disabled!\n"); + ret = 1; + } + if ((sio_read(port, 0x29) & 0x10) != 0) { + msg_perr("IT8705 flash write enable pin disabled!\n"); + ret = 1; + } + if ((sio_read(port, 0x29) & 0x08) != 0) { + msg_perr("IT8705 flash chip select pin disabled!\n"); + ret = 1; + } + if ((sio_read(port, 0x29) & 0x04) != 0) { + msg_perr("IT8705 flash read strobe pin disabled!\n"); + ret = 1; + } + if ((sio_read(port, 0x29) & 0x03) != 0) { + msg_perr("IT8705 flash address pins 16-17 disabled!\n"); + ret = 1; + } + if ((sio_read(port, 0x29) & 0x08) != 0) { + msg_perr("IT8705 flash pin disabled!\n"); + ret = 1; + } + msg_pdbg("Maximum IT8705 parallel flash decode size is %u\n", + max_rom_decode.parallel); + if (ret) { + msg_pinfo("Not enabling IT8705 flash write.\n"); + } else { + sio_write(port, 0x24, tmp); + } + } else { + msg_pdbg("No IT8705 flash segment enabled.\n"); + /* Not sure if this is an error or not. */ + ret = 0; + } exit_conf_mode_ite(port); - return 0; + return ret; } -/** - * Suited for: - * - AOpen vKM400Am-S: VIA KM400 + VT8237 + IT8705F. - * - Biostar P4M80-M4: VIA P4M800 + VT8237 + IT8705AF - * - Elitegroup K7S6A: SiS745 + ITE IT8705F - * - Elitegroup K7VTA3: VIA Apollo KT266/A/333 + VIA VT8235 + ITE IT8705F - * - GIGABYTE GA-7VT600: VIA KT600 + VT8237 + IT8705 - * - Shuttle AK38N: VIA KT333CF + VIA VT8235 + ITE IT8705F - * - * The SIS950 Super I/O probably requires the same flash write enable. - */ -static int it8705f_write_enable_2e(const char *name) -{ - return it8705f_write_enable(0x2e, name); -} - static int pc87360_gpio_set(uint8_t gpio, int raise) { static const int bankbase[] = {0, 4, 8, 10, 12}; @@ -1436,7 +1495,6 @@ {0x105a, 0x0d30, 0x105a, 0x4d33, 0x8086, 0x1130, 0x8086, 0, NULL, NULL, NULL, "Acorp", "6A815EPD", 0, OK, board_acorp_6a815epd}, {0x1022, 0x746B, 0, 0, 0, 0, 0, 0, NULL, "AGAMI", "ARUMA", "agami", "Aruma", 0, OK, w83627hf_gpio24_raise_2e}, {0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, NULL, "Albatron", "PM266A Pro", 0, OK, w836xx_memw_enable_2e}, - {0x1106, 0x3205, 0x1106, 0x3205, 0x10EC, 0x8139, 0xA0A0, 0x0477, NULL, NULL, NULL, "AOpen", "vKM400Am-S", 0, OK, it8705f_write_enable_2e}, {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe61", "Artec Group", "DBE61", 0, OK, board_artecgroup_dbe6x}, {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe62", "Artec Group", "DBE62", 0, OK, board_artecgroup_dbe6x}, {0x8086, 0x24D4, 0x1849, 0x24D0, 0x8086, 0x24D5, 0x1849, 0x9739, NULL, NULL, NULL, "ASRock", "P4i65GV", 0, OK, intel_ich_gpio23_raise}, @@ -1456,14 +1514,11 @@ {0x8086, 0x2570, 0x1043, 0x80F2, 0x105A, 0x3373, 0x1043, 0x80F5, NULL, NULL, NULL, "ASUS", "P4P800-E Deluxe", 0, OK, intel_ich_gpio21_raise}, {0x10B9, 0x1541, 0, 0, 0x10B9, 0x1533, 0, 0, "^P5A$", "asus", "p5a", "ASUS", "P5A", 0, OK, board_asus_p5a}, {0x10DE, 0x0030, 0x1043, 0x818a, 0x8086, 0x100E, 0x1043, 0x80EE, NULL, NULL, NULL, "ASUS", "P5ND2-SLI Deluxe", 0, OK, nvidia_mcp_gpio10_raise}, - {0x1106, 0x3149, 0x1565, 0x3206, 0x1106, 0x3344, 0x1565, 0x1202, NULL, NULL, NULL, "Biostar", "P4M80-M4", 0, OK, it8705f_write_enable_2e}, {0x8086, 0x3590, 0x1028, 0x016c, 0x1000, 0x0030, 0x1028, 0x016c, NULL, NULL, NULL, "Dell", "PowerEdge 1850", 0, OK, intel_ich_gpio23_raise}, - {0x1039, 0x5513, 0x1019, 0x0A41, 0x1039, 0x0018, 0, 0, NULL, NULL, NULL, "Elitegroup", "K7S6A", 0, OK, it8705f_write_enable_2e}, - {0x1106, 0x3038, 0x1019, 0x0996, 0x1106, 0x3177, 0x1019, 0x0996, NULL, NULL, NULL, "Elitegroup", "K7VTA3", 256, OK, it8705f_write_enable_2e}, + {0x1106, 0x3038, 0x1019, 0x0996, 0x1106, 0x3177, 0x1019, 0x0996, NULL, NULL, NULL, "Elitegroup", "K7VTA3", 256, OK, NULL}, {0x1106, 0x3177, 0x1106, 0x3177, 0x1106, 0x3059, 0x1695, 0x3005, NULL, NULL, NULL, "EPoX", "EP-8K5A2", 0, OK, w836xx_memw_enable_2e}, {0x10EC, 0x8139, 0x1695, 0x9001, 0x11C1, 0x5811, 0x1695, 0x9015, NULL, NULL, NULL, "EPoX", "EP-8RDA3+", 0, OK, nvidia_mcp_gpio31_raise}, {0x8086, 0x7110, 0, 0, 0x8086, 0x7190, 0, 0, NULL, "epox", "ep-bx3", "EPoX", "EP-BX3", 0, OK, board_epox_ep_bx3}, - {0x1106, 0x3227, 0x1458, 0x5001, 0x10ec, 0x8139, 0x1458, 0xe000, NULL, NULL, NULL, "GIGABYTE", "GA-7VT600", 0, OK, it8705f_write_enable_2e}, {0x1106, 0x0686, 0x1106, 0x0686, 0x1106, 0x3058, 0x1458, 0xa000, NULL, NULL, NULL, "GIGABYTE", "GA-7ZM", 512, OK, NULL}, {0x10DE, 0x0050, 0x1458, 0x0C11, 0x10DE, 0x005e, 0x1458, 0x5000, NULL, NULL, NULL, "GIGABYTE", "GA-K8N-SLI", 0, OK, nvidia_mcp_gpio21_raise}, {0x1166, 0x0223, 0x103c, 0x320d, 0x102b, 0x0522, 0x103c, 0x31fa, NULL, "hp", "dl145_g3", "HP", "DL145 G3", 0, OK, board_hp_dl145_g3_enable}, @@ -1487,7 +1542,7 @@ {0x10DE, 0x0270, 0x1462, 0x7207, 0x10DE, 0x0264, 0x1462, 0x7207, NULL, NULL, NULL, "MSI", "MS-7207 (K8N GM2-L)", 0, NT, nvidia_mcp_gpio2_raise}, {0x1011, 0x0019, 0xaa55, 0xaa55, 0x8086, 0x7190, 0, 0, NULL, NULL, NULL, "Nokia", "IP530", 0, OK, fdc37b787_gpio50_raise_3f0}, {0x1106, 0x3099, 0, 0, 0x1106, 0x3074, 0, 0, NULL, "shuttle", "ak31", "Shuttle", "AK31", 0, OK, w836xx_memw_enable_2e}, - {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, NULL, "Shuttle", "AK38N", 256, OK, it8705f_write_enable_2e}, + {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, NULL, "Shuttle", "AK38N", 256, OK, NULL}, {0x10DE, 0x0050, 0x1297, 0x5036, 0x1412, 0x1724, 0x1297, 0x5036, NULL, NULL, NULL, "Shuttle", "FN25", 0, OK, board_shuttle_fn25}, {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x3058, 0x15DD, 0x7609, NULL, NULL, NULL, "Soyo", "SY-7VCA", 0, OK, via_apollo_gpo0_lower}, {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x0596, 0x1106, 0, NULL, NULL, NULL, "Tekram", "P6Pro-A5", 256, OK, NULL}, -- http://www.hailfinger.org/

4 12

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flashrom June 2010