Change in flashrom[master]: [NOTFORMERGE] Add board enable for ASUS M3N78-EM.

[Nico Huber (Code Review)]

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/25115

Change subject: [NOTFORMERGE] Add board enable for ASUS M3N78-EM.
......................................................................

[NOTFORMERGE] Add board enable for ASUS M3N78-EM.

This does not work* (yet), but we want to keep it in patchwork for
further refinement.

* http://paste.flashrom.org/view.php?id=954

Change-Id: Id226d5f43f5966a0fd42613a5461bcdd9f6c7a8a
---
M board_enable.c
M chipset_enable.c
M mcp6x_spi.c
3 files changed, 37 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/flashrom refs/changes/15/25115/1

diff --git a/board_enable.c b/board_enable.c
index a6ee19f..c5e10d6 100644
--- a/board_enable.c
+++ b/board_enable.c
@@ -876,6 +876,17 @@
    return ret;
 }

+static int board_asus_m3n78em_enable(void)
+{
+	uint8_t tmp;
+
+	tmp = INB(0xA02);
+	tmp |= 0x01;
+	OUTB(tmp, 0xA02);
+
+	return 0;
+}
+
 /*
  * Suited for:
  *  - ASUS P5A
@@ -2341,6 +2352,7 @@
    {0x10de, 0x0264, 0x1043, 0x81bc,  0x10de, 0x02f0, 0x1043, 0x81cd, NULL,         NULL, NULL,           P3, "ASUS",        "A8N-VM CSM",            0,   OK, w83627ehf_gpio22_raise_2e},
    {0x10DE, 0x0264, 0x1043, 0x81C0,  0x10DE, 0x0260, 0x1043, 0x81C0, NULL,         NULL, NULL,           P3, "ASUS",        "M2NBP-VM CSM",          0,   OK, nvidia_mcp_gpio0_raise},
    {0x1106, 0x1336, 0x1043, 0x80ed,  0x1106, 0x3288, 0x1043, 0x8249, NULL,         NULL, NULL,           P3, "ASUS",        "M2V-MX",                0,   OK, via_vt823x_gpio5_raise},
+	{0x10de, 0x075c, 0x1043, 0x82f2,  0x10de, 0x0752, 0x1043, 0x82f2, NULL,         NULL, NULL,           P3, "ASUS",        "M3N78-EM",              0,   OK, board_asus_m3n78em_enable},
    {0x8086, 0x24cc,      0,      0,  0x8086, 0x24c3, 0x1043, 0x1869, "^M6Ne$",     NULL, NULL,           P3, "ASUS",        "M6Ne",                  0,   NT, intel_ich_gpio43_raise},
    {0x8086, 0x7180,      0,      0,  0x8086, 0x7110,      0,      0, "^OPLX-M$",   NULL, NULL,           P3, "ASUS",        "OPLX-M",                0,   NT, intel_piix4_gpo18_lower},
    {0x8086, 0x7190,      0,      0,  0x8086, 0x7110,      0,      0, "^P2B-N$",    NULL, NULL,           P3, "ASUS",        "P2B-N",                 0,   OK, intel_piix4_gpo18_lower},
diff --git a/chipset_enable.c b/chipset_enable.c
index 39e59dd..95b5b32 100644
--- a/chipset_enable.c
+++ b/chipset_enable.c
@@ -1105,6 +1105,8 @@

msg_pinfo("This chipset is not really supported yet. Guesswork...\n");

+	ret = enable_flash_mcp55(dev, name);
+
    /* dev is the ISA bridge. No idea what the stuff below does. */
    val = pci_read_byte(dev, 0x8a);
    msg_pdbg("ISA/LPC bridge reg 0x8a contents: 0x%02x, bit 6 is %i, bit 5 "
@@ -1112,7 +1114,6 @@

switch ((val >> 5) & 0x3) {
    case 0x0:
-		ret = enable_flash_mcp55(dev, name);
    	internal_buses_supported = BUS_LPC;
    	msg_pdbg("Flash bus type is LPC\n");
    	break;
@@ -1146,6 +1147,18 @@
    if (mcp6x_spi_init(want_spi))
    	ret = 1;

+	rpci_write_byte(dev, 0x8e, 0x00);
+	if (pci_read_byte(dev, 0x8e) != 0x00) {
+		msg_pinfo("Setting register 0x%x to 0x%x on %s failed "
+			  "(WARNING ONLY).\n", 0x8e, 0x00, name);
+	}
+
+	rpci_write_byte(dev, 0x8f, 0x00);
+	if (pci_read_byte(dev, 0x8f) != 0x00) {
+		msg_pinfo("Setting register 0x%x to 0x%x on %s failed "
+			  "(WARNING ONLY).\n", 0x8f, 0x00, name);
+	}
+
 out_msg:
    msg_pinfo("Please send the output of "flashrom -V" to "
    	  "[e-mail] with\n"
diff --git a/mcp6x_spi.c b/mcp6x_spi.c
index ac40557..abe8e0d 100644
--- a/mcp6x_spi.c
+++ b/mcp6x_spi.c
@@ -104,6 +104,7 @@

int mcp6x_spi_init(int want_spi)
 {
+	uint8_t old, new;
    uint16_t status;
    uint32_t mcp6x_spibaraddr;
    struct pci_dev *smbusdev;
@@ -125,6 +126,16 @@
    	smbusdev->bus, smbusdev->dev, smbusdev->func);

+	old = pci_read_byte(smbusdev, 0xe7);
+	new = old | 0x80;
+	if (new != old) {
+		rpci_write_byte(smbusdev, 0xe7, new);
+		if (pci_read_byte(smbusdev, 0xe7) != new) {
+			msg_pinfo("Setting register 0x%x to 0x%x failed "
+				  "(WARNING ONLY).\n", 0xe7, new);
+		}
+	}
+
    /* Locate the BAR where the SPI interface lives. */
    mcp6x_spibaraddr = pci_read_long(smbusdev, 0x74);
    /* BAR size is 64k, bits 15..4 are zero, bit 3..0 declare a