Attention is currently required from: Anastasia Klimchuk, Hsuan Ting Chen, Stefan Reinauer.
Hsuan-ting Chen has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/81356?usp=email )
Change subject: ich: Add names for region 5, 9, 10, 11, 12, 13, 15 ......................................................................
Patch Set 1:
(3 comments)
Commit Message:
https://review.coreboot.org/c/flashrom/+/81356/comment/64e08be4_fc4f7d5c : PS1, Line 12: * Incorporate missing region names from https://github.com/coreboot/coreboot/blob/main/util/ifdtool/ifdtool.c for completeness.
Thank you for syncing region names in two places! I am curious, is there any official doc from Intel […]
I believe there should be a document with its name like 'MTL SPI Programming Guide,' but I don't think it's publicly accessible. (I'm afraid I can't share anything since I don't have access myself.)
Perhaps Subrata could share some knowledge about where are those region names?
Patchset:
PS1: Hi Subrata:
Could you share if there's any basic knowledge about how Intel introduce those region names?
File ich_descriptors.c:
https://review.coreboot.org/c/flashrom/+/81356/comment/e0df6408_081eda1f : PS1, Line 521: msg_pdbg2(" FD BIOS ME GbE Pltf DE BIOS2 Reg7 EC DE2 ");
For this line (and diffs below in this file) you have changed the number of spaces between names? So […]
Yes, we used to pad names to 4 characters (lines 534 and 538). However, some newer names like '10GbE0' are too long.
To accommodate this, I now pad all names to 6 characters (with center alignment).
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Hsuan-ting Chen (Code Review)