Change in flashrom[master]: ichspi: Add Alder Lake support

[Edward O'Callaghan (Code Review)]

Edward O'Callaghan has submitted this change. ( https://review.coreboot.org/c/flashrom/+/62251 )

Change subject: ichspi: Add Alder Lake support
......................................................................

ichspi: Add Alder Lake support

Does exactly what it says on the tin.

BUG=b:220799648
TEST=```localhost ~ # flashrom --flash-name
<snip>
Found Programmer flash chip "Opaque flash chip" (32768 kB, Programmer-specific) mapped at physical address 0x0000000000000000.
vendor="Programmer" name="Opaque flash chip"

flashrom -p internal --ifd -i fd -i bios -r /tmp/filename.rom
flashrom unknown on Linux 5.15.22 (x86_64)
flashrom is free software, get the source code at https://flashrom.org

Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns).
coreboot table found at 0x768a7000.
Found chipset "Intel Alder Lake-N".
Enabling flash write... Warning: Setting BIOS Control at 0xdc from 0x8b to 0x89 failed.
New value is 0x8b.
SPI Configuration is locked down.
OK.
Found Winbond flash chip "W25Q256JV_M" (32768 kB, Programmer-specific) mapped at physical address 0x0000000000000000.
Error accessing W25Q256JV_M, 0x2000000 bytes at 0x00000000fe000000
/dev/mem mmap failed: Resource temporarily unavailable
Could not map flash chip W25Q256JV_M at 0x00000000fe000000.
Reading ich descriptor... done.
Using regions: "bios", "fd".
Error accessing W25Q256JV_M, 0x2000000 bytes at 0x00000000fe000000
/dev/mem mmap failed: Resource temporarily unavailable
Could not map flash chip W25Q256JV_M at 0x00000000fe000000.
Reading flash... done.
SUCCESS

Also,
Reading ich descriptor... Reading 4096 bytes starting at 0x000000.
done.
Assuming chipset '600 series Alder Point'.
Added layout entry 00000000 - 00000fff named fd
Added layout entry 00500000 - 01ffffff named bios
Added layout entry 00001000 - 004fffff named me
```
Tested on Nivviks/ADL-N and Brya/ADL-P.

Change-Id: Ie66cf519df13f3391c41f5016b16a81ef3dfd4bf
Signed-off-by: Edward O'Callaghan 
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62251
Tested-by: build bot (Jenkins) 
Reviewed-by: Subrata Banik 
Reviewed-by: Sam McNally 
---
M chipset_enable.c
M ich_descriptors.c
M ichspi.c
M programmer.h
M util/ich_descriptors_tool/ich_descriptors_tool.c
5 files changed, 34 insertions(+), 3 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Sam McNally: Looks good to me, approved
  Subrata Banik: Looks good to me, approved

diff --git a/chipset_enable.c b/chipset_enable.c
index d4285a5..ac9377b 100644
--- a/chipset_enable.c
+++ b/chipset_enable.c
@@ -605,6 +605,7 @@
    case CHIPSET_300_SERIES_CANNON_POINT:
    case CHIPSET_400_SERIES_COMET_POINT:
    case CHIPSET_500_SERIES_TIGER_POINT:
+	case CHIPSET_600_SERIES_ALDER_POINT:
    case CHIPSET_ELKHART_LAKE:
    case CHIPSET_APOLLO_LAKE:
    case CHIPSET_GEMINI_LAKE:
@@ -709,6 +710,7 @@
    	boot_straps = boot_straps_pch8_lp;
    	break;
    case CHIPSET_500_SERIES_TIGER_POINT:
+	case CHIPSET_600_SERIES_ALDER_POINT:
    	boot_straps = boot_straps_pch500;
    	break;
    case CHIPSET_APOLLO_LAKE:
@@ -741,6 +743,7 @@
    case CHIPSET_300_SERIES_CANNON_POINT:
    case CHIPSET_400_SERIES_COMET_POINT:
    case CHIPSET_500_SERIES_TIGER_POINT:
+	case CHIPSET_600_SERIES_ALDER_POINT:
    case CHIPSET_APOLLO_LAKE:
    case CHIPSET_GEMINI_LAKE:
    case CHIPSET_ELKHART_LAKE:
@@ -994,6 +997,11 @@
    return enable_flash_pch100_or_c620(dev, name, 0x1f, 5, CHIPSET_500_SERIES_TIGER_POINT);
 }

+static int enable_flash_pch600(struct pci_dev *const dev, const char *const name)
+{
+	return enable_flash_pch100_or_c620(dev, name, 0x1f, 5, CHIPSET_600_SERIES_ALDER_POINT);
+}
+
 static int enable_flash_mcc(struct pci_dev *const dev, const char *const name)
 {
    return enable_flash_pch100_or_c620(dev, name, 0x1f, 5, CHIPSET_ELKHART_LAKE);
@@ -2141,6 +2149,8 @@
    {0x8086, 0x4389, B_S,    NT,  "Intel", "WM590",				enable_flash_pch500},
    {0x8086, 0x438a, B_S,    NT,  "Intel", "QM580",				enable_flash_pch500},
    {0x8086, 0x438b, B_S,    DEP, "Intel", "HM570",				enable_flash_pch500},
+	{0x8086, 0x54a4, B_S,    DEP, "Intel", "Alder Lake-N",			enable_flash_pch600},
+	{0x8086, 0x51a4, B_S,    DEP, "Intel", "Alder Lake-P",			enable_flash_pch600},
 #endif
    {0},
 };
diff --git a/ich_descriptors.c b/ich_descriptors.c
index 0ce5720..256224d 100644
--- a/ich_descriptors.c
+++ b/ich_descriptors.c
@@ -46,6 +46,7 @@
    case CHIPSET_300_SERIES_CANNON_POINT:
    case CHIPSET_400_SERIES_COMET_POINT:
    case CHIPSET_500_SERIES_TIGER_POINT:
+	case CHIPSET_600_SERIES_ALDER_POINT:
    case CHIPSET_ELKHART_LAKE:
    	return 16;
    case CHIPSET_100_SERIES_SUNRISE_POINT:
@@ -72,6 +73,7 @@
    switch (cs) {
    case CHIPSET_C620_SERIES_LEWISBURG:
    case CHIPSET_APOLLO_LAKE:
+	case CHIPSET_600_SERIES_ALDER_POINT:
    case CHIPSET_GEMINI_LAKE:
    case CHIPSET_ELKHART_LAKE:
    	if (cont->NM <= MAX_NUM_MASTERS)
@@ -111,7 +113,7 @@
    	"8 series Lynx Point", "Baytrail", "8 series Lynx Point LP", "8 series Wellsburg",
    	"9 series Wildcat Point", "9 series Wildcat Point LP", "100 series Sunrise Point",
    	"C620 series Lewisburg", "300 series Cannon Point", "400 series Comet Point",
-		"500 series Tiger Point", "Apollo Lake", "Gemini Lake", "Elkhart Lake",
+		"500 series Tiger Point", "600 series Alder Point", "Apollo Lake", "Gemini Lake", "Elkhart Lake",
    };
    if (cs < CHIPSET_ICH8 || cs - CHIPSET_ICH8 + 1 >= ARRAY_SIZE(chipset_names))
    	cs = 0;
@@ -206,6 +208,7 @@
    case CHIPSET_300_SERIES_CANNON_POINT:
    case CHIPSET_400_SERIES_COMET_POINT:
    case CHIPSET_500_SERIES_TIGER_POINT:
+	case CHIPSET_600_SERIES_ALDER_POINT:
    case CHIPSET_APOLLO_LAKE:
    case CHIPSET_GEMINI_LAKE:
    case CHIPSET_ELKHART_LAKE: {
@@ -300,6 +303,7 @@
    case CHIPSET_GEMINI_LAKE:
    	return freq_str[2][value];
    case CHIPSET_500_SERIES_TIGER_POINT:
+	case CHIPSET_600_SERIES_ALDER_POINT:
    	return freq_str[3][value];
    case CHIPSET_ELKHART_LAKE:
    	return freq_str[4][value];
@@ -346,6 +350,7 @@
    case CHIPSET_300_SERIES_CANNON_POINT:
    case CHIPSET_400_SERIES_COMET_POINT:
    case CHIPSET_500_SERIES_TIGER_POINT:
+	case CHIPSET_600_SERIES_ALDER_POINT:
    case CHIPSET_APOLLO_LAKE:
    case CHIPSET_GEMINI_LAKE:
    case CHIPSET_ELKHART_LAKE:
@@ -470,7 +475,8 @@
    if (cs == CHIPSET_100_SERIES_SUNRISE_POINT ||
        cs == CHIPSET_300_SERIES_CANNON_POINT ||
        cs == CHIPSET_400_SERIES_COMET_POINT ||
-	    cs == CHIPSET_500_SERIES_TIGER_POINT) {
+	    cs == CHIPSET_500_SERIES_TIGER_POINT ||
+	    cs == CHIPSET_600_SERIES_ALDER_POINT) {
    	const char *const master_names[] = {
    		"BIOS", "ME", "GbE", "unknown", "EC",
    	};
@@ -1031,6 +1037,8 @@
    		return CHIPSET_300_SERIES_CANNON_POINT;
    	if (content->CSSL == 0x11)
    		return CHIPSET_500_SERIES_TIGER_POINT;
+		if (content->CSSL == 0x14)
+			return CHIPSET_600_SERIES_ALDER_POINT;
    	if (content->CSSL == 0x03)
    		return CHIPSET_ELKHART_LAKE;
    	msg_pwarn("Unknown flash descriptor, assuming 500 series compatibility.\n");
@@ -1054,6 +1062,7 @@
    case CHIPSET_300_SERIES_CANNON_POINT:
    case CHIPSET_400_SERIES_COMET_POINT:
    case CHIPSET_500_SERIES_TIGER_POINT:
+	case CHIPSET_600_SERIES_ALDER_POINT:
    case CHIPSET_GEMINI_LAKE:
    case CHIPSET_ELKHART_LAKE:
    	/* `freq_read` was repurposed, so can't check on it any more. */
@@ -1210,6 +1219,7 @@
    case CHIPSET_300_SERIES_CANNON_POINT:
    case CHIPSET_400_SERIES_COMET_POINT:
    case CHIPSET_500_SERIES_TIGER_POINT:
+	case CHIPSET_600_SERIES_ALDER_POINT:
    case CHIPSET_APOLLO_LAKE:
    case CHIPSET_GEMINI_LAKE:
    case CHIPSET_ELKHART_LAKE:
@@ -1249,6 +1259,7 @@
    case CHIPSET_300_SERIES_CANNON_POINT:
    case CHIPSET_400_SERIES_COMET_POINT:
    case CHIPSET_500_SERIES_TIGER_POINT:
+	case CHIPSET_600_SERIES_ALDER_POINT:
    case CHIPSET_APOLLO_LAKE:
    case CHIPSET_GEMINI_LAKE:
    case CHIPSET_ELKHART_LAKE:
diff --git a/ichspi.c b/ichspi.c
index 117ff8d..84ac035 100644
--- a/ichspi.c
+++ b/ichspi.c
@@ -1781,6 +1781,7 @@
    case CHIPSET_300_SERIES_CANNON_POINT:
    case CHIPSET_400_SERIES_COMET_POINT:
    case CHIPSET_500_SERIES_TIGER_POINT:
+	case CHIPSET_600_SERIES_ALDER_POINT:
    case CHIPSET_APOLLO_LAKE:
    case CHIPSET_GEMINI_LAKE:
    case CHIPSET_ELKHART_LAKE:
@@ -1817,6 +1818,7 @@
    case CHIPSET_300_SERIES_CANNON_POINT:
    case CHIPSET_400_SERIES_COMET_POINT:
    case CHIPSET_500_SERIES_TIGER_POINT:
+	case CHIPSET_600_SERIES_ALDER_POINT:
    case CHIPSET_APOLLO_LAKE:
    case CHIPSET_GEMINI_LAKE:
    case CHIPSET_ELKHART_LAKE:
@@ -1875,6 +1877,7 @@
    case CHIPSET_300_SERIES_CANNON_POINT:
    case CHIPSET_400_SERIES_COMET_POINT:
    case CHIPSET_500_SERIES_TIGER_POINT:
+	case CHIPSET_600_SERIES_ALDER_POINT:
    case CHIPSET_APOLLO_LAKE:
    case CHIPSET_GEMINI_LAKE:
    case CHIPSET_ELKHART_LAKE:
@@ -1952,6 +1955,7 @@
    	case CHIPSET_300_SERIES_CANNON_POINT:
    	case CHIPSET_400_SERIES_COMET_POINT:
    	case CHIPSET_500_SERIES_TIGER_POINT:
+		case CHIPSET_600_SERIES_ALDER_POINT:
    	case CHIPSET_APOLLO_LAKE:
    	case CHIPSET_GEMINI_LAKE:
    	case CHIPSET_BAYTRAIL:
@@ -1988,6 +1992,7 @@
    	case CHIPSET_300_SERIES_CANNON_POINT:
    	case CHIPSET_400_SERIES_COMET_POINT:
    	case CHIPSET_500_SERIES_TIGER_POINT:
+		case CHIPSET_600_SERIES_ALDER_POINT:
    	case CHIPSET_APOLLO_LAKE:
    	case CHIPSET_GEMINI_LAKE:
    	case CHIPSET_ELKHART_LAKE:
@@ -2022,7 +2027,8 @@
        (ich_gen == CHIPSET_100_SERIES_SUNRISE_POINT ||
         ich_gen == CHIPSET_300_SERIES_CANNON_POINT ||
         ich_gen == CHIPSET_400_SERIES_COMET_POINT ||
-	     ich_gen == CHIPSET_500_SERIES_TIGER_POINT)) {
+	     ich_gen == CHIPSET_500_SERIES_TIGER_POINT ||
+	     ich_gen == CHIPSET_600_SERIES_ALDER_POINT)) {
    	msg_pdbg("Enabling hardware sequencing by default for 100+ series PCH.\n");
    	ich_spi_mode = ich_hwseq;
    }
diff --git a/programmer.h b/programmer.h
index 9305afb..6a0c3fa 100644
--- a/programmer.h
+++ b/programmer.h
@@ -353,6 +353,7 @@
    CHIPSET_300_SERIES_CANNON_POINT,
    CHIPSET_400_SERIES_COMET_POINT,
    CHIPSET_500_SERIES_TIGER_POINT,
+	CHIPSET_600_SERIES_ALDER_POINT,
    CHIPSET_APOLLO_LAKE,
    CHIPSET_GEMINI_LAKE,
    CHIPSET_ELKHART_LAKE,
diff --git a/util/ich_descriptors_tool/ich_descriptors_tool.c b/util/ich_descriptors_tool/ich_descriptors_tool.c
index f743510..532a1fb 100644
--- a/util/ich_descriptors_tool/ich_descriptors_tool.c
+++ b/util/ich_descriptors_tool/ich_descriptors_tool.c
@@ -137,6 +137,7 @@
 "\t- "300" or "cannon" for Intel's 300 series chipsets.\n"
 "\t- "400" or "comet" for Intel's 400 series chipsets.\n"
 "\t- "500" or "tiger" for Intel's 500 series chipsets.\n"
+"\t- "600" or "alder" for Intel's 600 series chipsets.\n"
 "If '-d' is specified some regions such as the BIOS image as seen by the CPU or\n"
 "the GbE blob that is required to initialize the GbE are also dumped to files.\n",
    argv[0], argv[0]);
@@ -234,6 +235,8 @@
    	else if ((strcmp(csn, "500") == 0) ||
    		 (strcmp(csn, "tiger") == 0))
    		cs = CHIPSET_500_SERIES_TIGER_POINT;
+		else if (strcmp(csn, "600") == 0)
+			cs = CHIPSET_600_SERIES_ALDER_POINT;
    	else if (strcmp(csn, "apollo") == 0)
    		cs = CHIPSET_APOLLO_LAKE;
    	else if (strcmp(csn, "gemini") == 0)