Attention is currently required from: Nico Huber, Angel Pons. Thomas Walker has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/52310 )
Change subject: flashchips: Add Spansion/Cypress S25FL256L ......................................................................
Patch Set 5:
(4 comments)
Patchset:
PS5: Removed incorrect macros, corrected block erase comment and added case for 0x53 opcode.
File spi.h:
https://review.coreboot.org/c/flashrom/+/52310/comment/428a90db_75260fb7 PS4, Line 93:
Block Erase 0x53 is only supported by Spansion/Cypress S25FL-L chips. […]
Done
File spi25.c:
https://review.coreboot.org/c/flashrom/+/52310/comment/effcc8f5_a79a1a2a PS4, Line 491: /* This usually takes 100-4000ms, so wait in 100ms steps. */
Datasheet for S25FL064L says typical is 300 ms, and maximum is 600 ms. Datasheet for S25FL256L says typical is 190 ms, and maximum is 363 ms.
Without checking any other datasheets, I'd say the 4000 ms in the comment could be lowered to 1000 ms.
Not a problem. Just out of curiosity, how do you best calculate the step size based on typical and max time?
https://review.coreboot.org/c/flashrom/+/52310/comment/dd51934c_8b84774b PS4, Line 621: return &spi_block_erase_52;
Add an entry here too?
Done