Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/28707
Change subject: Remove unneeded whitespace ......................................................................
Remove unneeded whitespace
Change-Id: I0e72e3e3736a39685b7f166c5e6b06cc241b26be Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M board_enable.c M cbtable.c M chipset_enable.c M drkaiser.c M flashchips.c M flashchips.h M flashrom.c M hwaccess.h M pickit2_spi.c 9 files changed, 186 insertions(+), 186 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/07/28707/1
diff --git a/board_enable.c b/board_enable.c index 9d45813..d1c9da5 100644 --- a/board_enable.c +++ b/board_enable.c @@ -156,7 +156,7 @@ const struct winbond_mux *mux; /* NULL or pointer to mux info for the 8 bits */ uint8_t ldn; /* LDN this GPIO register is located in */ uint8_t enable_bit; /* bit in 0x30 of that LDN to enable - the GPIO port */ + the GPIO port */ uint8_t base; /* base register in that LDN for the port */ };
@@ -391,7 +391,7 @@ * soon as we have generic Super I/O detection code. */ static int winbond_gpio_set(uint16_t base, enum winbond_id chipid, - int pin, int raise) + int pin, int raise) { const struct winbond_chip *chip = NULL; const struct winbond_port *gpio; @@ -405,12 +405,12 @@ } if (chip->device_id != chipid) { msg_perr("\nERROR: Found Winbond chip with ID 0x%x, " - "expected %x\n", chip->device_id, chipid); + "expected %x\n", chip->device_id, chipid); return -1; } if (bit >= 8 || port == 0 || port > chip->gpio_port_count) { msg_perr("\nERROR: winbond_gpio_set: Invalid GPIO number %d\n", - pin); + pin); return -1; }
@@ -418,7 +418,7 @@
if (gpio->ldn == 0) { msg_perr("\nERROR: GPIO%d is not supported yet on this" - " winbond chip\n", port); + " winbond chip\n", port); return -1; }
@@ -433,7 +433,7 @@ /* Select GPIO function of that pin. */ if (gpio->mux && gpio->mux[bit].reg) sio_mask(base, gpio->mux[bit].reg, - gpio->mux[bit].data, gpio->mux[bit].mask); + gpio->mux[bit].data, gpio->mux[bit].mask);
sio_mask(base, gpio->base + 0, 0, 1 << bit); /* Make pin output */ sio_mask(base, gpio->base + 2, 0, 1 << bit); /* Clear inversion */ @@ -1036,7 +1036,7 @@ LPC bridge, but have the same SMBus bridge IDs */ if (dev->func != 0) { msg_perr("MCP LPC bridge at unexpected function" - " number %d\n", dev->func); + " number %d\n", dev->func); return -1; }
@@ -1056,7 +1056,7 @@ devclass = pci_read_word(dev, PCI_CLASS_DEVICE); if (devclass != 0x0C05) { msg_perr("Unexpected device class %04x for SMBus" - " controller\n", devclass); + " controller\n", devclass); return -1; } break; @@ -1125,12 +1125,12 @@ * - HP xw9400 (Tyan S2915-E OEM): Dual(!) NVIDIA MCP55 * * Notes: a) There are two MCP55 chips, so also two SMBus bridges on that - * board. We can't tell the SMBus logical devices apart, but we - * can tell the LPC bridge functions apart. - * We need to choose the SMBus bridge next to the LPC bridge with - * ID 0x364 and the "LPC bridge" class. - * b) #TBL is hardwired on that board to a pull-down. It can be - * overridden by connecting the two solder points next to F2. + * board. We can't tell the SMBus logical devices apart, but we + * can tell the LPC bridge functions apart. + * We need to choose the SMBus bridge next to the LPC bridge with + * ID 0x364 and the "LPC bridge" class. + * b) #TBL is hardwired on that board to a pull-down. It can be + * overridden by connecting the two solder points next to F2. */ static int nvidia_mcp_gpio5_raise(void) { @@ -1329,35 +1329,35 @@
static const struct {unsigned int reg, mask, value; } piix4_gpo[] = { {0}, - {0xB0, 0x0001, 0x0000}, /* GPO1... */ + {0xB0, 0x0001, 0x0000}, /* GPO1... */ {0xB0, 0x0001, 0x0000}, {0xB0, 0x0001, 0x0000}, {0xB0, 0x0001, 0x0000}, {0xB0, 0x0001, 0x0000}, {0xB0, 0x0001, 0x0000}, - {0xB0, 0x0001, 0x0000}, /* ...GPO7: GENCFG bit 0 */ + {0xB0, 0x0001, 0x0000}, /* ...GPO7: GENCFG bit 0 */ {0}, - {0xB0, 0x0100, 0x0000}, /* GPO9: GENCFG bit 8 */ - {0xB0, 0x0200, 0x0000}, /* GPO10: GENCFG bit 9 */ - {0xB0, 0x0400, 0x0000}, /* GPO11: GENCFG bit 10 */ - {0x4E, 0x0100, 0x0000}, /* GPO12... */ + {0xB0, 0x0100, 0x0000}, /* GPO9: GENCFG bit 8 */ + {0xB0, 0x0200, 0x0000}, /* GPO10: GENCFG bit 9 */ + {0xB0, 0x0400, 0x0000}, /* GPO11: GENCFG bit 10 */ + {0x4E, 0x0100, 0x0000}, /* GPO12... */ {0x4E, 0x0100, 0x0000}, - {0x4E, 0x0100, 0x0000}, /* ...GPO14: XBCS bit 8 */ - {0xB2, 0x0002, 0x0002}, /* GPO15... */ - {0xB2, 0x0002, 0x0002}, /* ...GPO16: GENCFG bit 17 */ - {0xB2, 0x0004, 0x0004}, /* GPO17: GENCFG bit 18 */ - {0xB2, 0x0008, 0x0008}, /* GPO18: GENCFG bit 19 */ - {0xB2, 0x0010, 0x0010}, /* GPO19: GENCFG bit 20 */ - {0xB2, 0x0020, 0x0020}, /* GPO20: GENCFG bit 21 */ - {0xB2, 0x0040, 0x0040}, /* GPO21: GENCFG bit 22 */ - {0xB2, 0x1000, 0x1000}, /* GPO22... */ - {0xB2, 0x1000, 0x1000}, /* ...GPO23: GENCFG bit 28 */ - {0xB2, 0x2000, 0x2000}, /* GPO24: GENCFG bit 29 */ - {0xB2, 0x4000, 0x4000}, /* GPO25: GENCFG bit 30 */ - {0xB2, 0x8000, 0x8000}, /* GPO26: GENCFG bit 31 */ + {0x4E, 0x0100, 0x0000}, /* ...GPO14: XBCS bit 8 */ + {0xB2, 0x0002, 0x0002}, /* GPO15... */ + {0xB2, 0x0002, 0x0002}, /* ...GPO16: GENCFG bit 17 */ + {0xB2, 0x0004, 0x0004}, /* GPO17: GENCFG bit 18 */ + {0xB2, 0x0008, 0x0008}, /* GPO18: GENCFG bit 19 */ + {0xB2, 0x0010, 0x0010}, /* GPO19: GENCFG bit 20 */ + {0xB2, 0x0020, 0x0020}, /* GPO20: GENCFG bit 21 */ + {0xB2, 0x0040, 0x0040}, /* GPO21: GENCFG bit 22 */ + {0xB2, 0x1000, 0x1000}, /* GPO22... */ + {0xB2, 0x1000, 0x1000}, /* ...GPO23: GENCFG bit 28 */ + {0xB2, 0x2000, 0x2000}, /* GPO24: GENCFG bit 29 */ + {0xB2, 0x4000, 0x4000}, /* GPO25: GENCFG bit 30 */ + {0xB2, 0x8000, 0x8000}, /* GPO26: GENCFG bit 31 */ {0}, {0}, - {0x4E, 0x0100, 0x0000}, /* ...GPO29: XBCS bit 8 */ + {0x4E, 0x0100, 0x0000}, /* ...GPO29: XBCS bit 8 */ {0} };
@@ -1994,7 +1994,7 @@ * Returns the base port of the runtime register block, or 0 on error. */ static uint16_t smsc_find_runtime(uint16_t sio_port, uint16_t chip_id, - uint8_t logical_device) + uint8_t logical_device) { uint16_t rt_port = 0;
@@ -2009,7 +2009,7 @@ sio_write(sio_port, 0x07, logical_device); if (sio_read(sio_port, 0x30) & 1) { rt_port = (sio_read(sio_port, 0x60) << 8) - | sio_read(sio_port, 0x61); + | sio_read(sio_port, 0x61); }
if (rt_port == 0) { @@ -2043,12 +2043,12 @@
/* Configure the GPIO pin. */ val = INB(rt_port + 0x33); /* GP30 config */ - val &= ~0x87; /* Output, non-inverted, GPIO, push/pull */ + val &= ~0x87; /* Output, non-inverted, GPIO, push/pull */ OUTB(val, rt_port + 0x33);
/* Disable write protection. */ val = INB(rt_port + 0x4d); /* GP3 values */ - val |= 0x01; /* Set GP30 high. */ + val |= 0x01; /* Set GP30 high. */ OUTB(val, rt_port + 0x4d);
return 0; @@ -2262,7 +2262,7 @@ * flashrom before their ROM chip can be accessed/written to. * * NOTE: Please add boards that _don't_ need such enables or don't work yet - * to the respective tables in print.c. Thanks! + * to the respective tables in print.c. Thanks! * * We use 2 sets of PCI IDs here, you're free to choose which is which. This * is to provide a very high degree of certainty when matching a board on diff --git a/cbtable.c b/cbtable.c index fe0c368..827bebe 100644 --- a/cbtable.c +++ b/cbtable.c @@ -203,10 +203,10 @@ rec = (struct lb_mainboard *)ptr; max_size = rec->size - sizeof(*rec); msg_pdbg("Vendor ID: %.*s, part ID: %.*s\n", - max_size - rec->vendor_idx, - rec->strings + rec->vendor_idx, - max_size - rec->part_number_idx, - rec->strings + rec->part_number_idx); + max_size - rec->vendor_idx, + rec->strings + rec->vendor_idx, + max_size - rec->part_number_idx, + rec->strings + rec->part_number_idx); snprintf(vendor, 255, "%.*s", max_size - rec->vendor_idx, rec->strings + rec->vendor_idx); snprintf(part, 255, "%.*s", max_size - rec->part_number_idx, rec->strings + rec->part_number_idx);
diff --git a/chipset_enable.c b/chipset_enable.c index 566b1fb..fea4017 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -228,14 +228,14 @@ old = pci_read_word(dev, xbcs);
/* Set bit 9: 1-Meg Extended BIOS Enable (PCI master accesses to - * FFF00000-FFF7FFFF are forwarded to ISA). - * Note: This bit is reserved on PIIX/PIIX3/MPIIX. + * FFF00000-FFF7FFFF are forwarded to ISA). + * Note: This bit is reserved on PIIX/PIIX3/MPIIX. * Set bit 7: Extended BIOS Enable (PCI master accesses to - * FFF80000-FFFDFFFF are forwarded to ISA). + * FFF80000-FFFDFFFF are forwarded to ISA). * Set bit 6: Lower BIOS Enable (PCI master, or ISA master accesses to - * the lower 64-Kbyte BIOS block (E0000-EFFFF) at the top - * of 1 Mbyte, or the aliases at the top of 4 Gbyte - * (FFFE0000-FFFEFFFF) result in the generation of BIOSCS#. + * the lower 64-Kbyte BIOS block (E0000-EFFFF) at the top + * of 1 Mbyte, or the aliases at the top of 4 Gbyte + * (FFFE0000-FFFEFFFF) result in the generation of BIOSCS#. * Note: Accesses to FFFF0000-FFFFFFFF are always forwarded to ISA. * Set bit 2: BIOSCS# Write Enable (1=enable, 0=disable). */ diff --git a/drkaiser.c b/drkaiser.c index ac49df3..2fe294c 100644 --- a/drkaiser.c +++ b/drkaiser.c @@ -24,7 +24,7 @@ #define PCI_MAGIC_DRKAISER_ADDR 0x50 #define PCI_MAGIC_DRKAISER_VALUE 0xa971
-#define DRKAISER_MEMMAP_SIZE (1024 * 128) +#define DRKAISER_MEMMAP_SIZE (1024 * 128)
/* Mask to restrict flash accesses to the 128kB memory window. */ #define DRKAISER_MEMMAP_MASK ((1 << 17) - 1) diff --git a/flashchips.c b/flashchips.c index 2001d8c..b2d9611 100644 --- a/flashchips.c +++ b/flashchips.c @@ -15859,18 +15859,18 @@ },
{ - .vendor = "Winbond", - .name = "W25P80", - .bustype = BUS_SPI, - .manufacture_id = WINBOND_NEX_ID, - .model_id = WINBOND_NEX_W25P80, - .total_size = 1024, - .page_size = 256, - .feature_bits = FEATURE_WRSR_WREN, - .tested = TEST_UNTESTED, - .probe = probe_spi_rdid, - .probe_timing = TIMING_ZERO, - .block_erasers = + .vendor = "Winbond", + .name = "W25P80", + .bustype = BUS_SPI, + .manufacture_id = WINBOND_NEX_ID, + .model_id = WINBOND_NEX_W25P80, + .total_size = 1024, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = { { .eraseblocks = { {64 * 1024, 16} }, @@ -15880,26 +15880,26 @@ .block_erase = spi_block_erase_c7, } }, - .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ - .unlock = spi_disable_blockprotect, - .write = spi_chip_write_256, - .read = spi_chip_read, /* Fast read (0x0B) supported */ - .voltage = {2700, 3600}, + .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, /* Fast read (0x0B) supported */ + .voltage = {2700, 3600}, },
{ - .vendor = "Winbond", - .name = "W25P16", - .bustype = BUS_SPI, - .manufacture_id = WINBOND_NEX_ID, - .model_id = WINBOND_NEX_W25P16, - .total_size = 2048, - .page_size = 256, - .feature_bits = FEATURE_WRSR_WREN, - .tested = TEST_UNTESTED, - .probe = probe_spi_rdid, - .probe_timing = TIMING_ZERO, - .block_erasers = + .vendor = "Winbond", + .name = "W25P16", + .bustype = BUS_SPI, + .manufacture_id = WINBOND_NEX_ID, + .model_id = WINBOND_NEX_W25P16, + .total_size = 2048, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = { { .eraseblocks = { {64 * 1024, 32} }, @@ -15909,26 +15909,26 @@ .block_erase = spi_block_erase_c7, } }, - .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ - .unlock = spi_disable_blockprotect, - .write = spi_chip_write_256, - .read = spi_chip_read, /* Fast read (0x0B) supported */ - .voltage = {2700, 3600}, + .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, /* Fast read (0x0B) supported */ + .voltage = {2700, 3600}, },
{ - .vendor = "Winbond", - .name = "W25P32", - .bustype = BUS_SPI, - .manufacture_id = WINBOND_NEX_ID, - .model_id = WINBOND_NEX_W25P32, - .total_size = 4096, - .page_size = 256, - .feature_bits = FEATURE_WRSR_WREN, - .tested = TEST_UNTESTED, - .probe = probe_spi_rdid, - .probe_timing = TIMING_ZERO, - .block_erasers = + .vendor = "Winbond", + .name = "W25P32", + .bustype = BUS_SPI, + .manufacture_id = WINBOND_NEX_ID, + .model_id = WINBOND_NEX_W25P32, + .total_size = 4096, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = { { .eraseblocks = { {64 * 1024, 64} }, @@ -15938,11 +15938,11 @@ .block_erase = spi_block_erase_c7, } }, - .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ - .unlock = spi_disable_blockprotect, - .write = spi_chip_write_256, - .read = spi_chip_read, /* Fast read (0x0B) supported */ - .voltage = {2700, 3600}, + .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, /* Fast read (0x0B) supported */ + .voltage = {2700, 3600}, }, { .vendor = "Winbond", @@ -16760,18 +16760,18 @@ },
{ - .vendor = "Zetta Device", - .name = "ZD25D20", - .bustype = BUS_SPI, - .manufacture_id = ZETTADEVICE_ID, - .model_id = ZETTADEVICE_ZD25D20, - .total_size = 256, - .page_size = 256, - .feature_bits = FEATURE_WRSR_WREN, - .tested = TEST_UNTESTED, - .probe = probe_spi_rdid, - .probe_timing = TIMING_ZERO, - .block_erasers = + .vendor = "Zetta Device", + .name = "ZD25D20", + .bustype = BUS_SPI, + .manufacture_id = ZETTADEVICE_ID, + .model_id = ZETTADEVICE_ZD25D20, + .total_size = 256, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = { { .eraseblocks = { {4 * 1024, 64} }, @@ -16790,26 +16790,26 @@ .block_erase = spi_block_erase_c7, } }, - .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ - .unlock = spi_disable_blockprotect, - .write = spi_chip_write_256, - .read = spi_chip_read, - .voltage = {2700, 3600}, + .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2700, 3600}, },
{ - .vendor = "Zetta Device", - .name = "ZD25D40", - .bustype = BUS_SPI, - .manufacture_id = ZETTADEVICE_ID, - .model_id = ZETTADEVICE_ZD25D40, - .total_size = 512, - .page_size = 256, - .feature_bits = FEATURE_WRSR_WREN, - .tested = TEST_UNTESTED, - .probe = probe_spi_rdid, - .probe_timing = TIMING_ZERO, - .block_erasers = + .vendor = "Zetta Device", + .name = "ZD25D40", + .bustype = BUS_SPI, + .manufacture_id = ZETTADEVICE_ID, + .model_id = ZETTADEVICE_ZD25D40, + .total_size = 512, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, + .tested = TEST_UNTESTED, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = { { .eraseblocks = { {4 * 1024, 128} }, @@ -16828,11 +16828,11 @@ .block_erase = spi_block_erase_c7, } }, - .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ - .unlock = spi_disable_blockprotect, - .write = spi_chip_write_256, - .read = spi_chip_read, - .voltage = {2700, 3600}, + .printlock = spi_prettyprint_status_register_plain, /* TODO: improve */ + .unlock = spi_disable_blockprotect, + .write = spi_chip_write_256, + .read = spi_chip_read, + .voltage = {2700, 3600}, },
{ diff --git a/flashchips.h b/flashchips.h index ecd8d7a..aff6915 100644 --- a/flashchips.h +++ b/flashchips.h @@ -964,8 +964,8 @@ #define WINBOND_W49V002A 0xB0 #define WINBOND_W49V002FA 0x32
-#define ZETTADEVICE_ID 0xBA /* Zetta Device */ -#define ZETTADEVICE_ZD25D20 0x2012 -#define ZETTADEVICE_ZD25D40 0x2013 +#define ZETTADEVICE_ID 0xBA /* Zetta Device */ +#define ZETTADEVICE_ZD25D20 0x2012 +#define ZETTADEVICE_ZD25D40 0x2013
#endif /* !FLASHCHIPS_H */ diff --git a/flashrom.c b/flashrom.c index 094630c..921e556 100644 --- a/flashrom.c +++ b/flashrom.c @@ -792,7 +792,7 @@
/* Helper function for need_erase() that focuses on granularities of gran bytes. */ static int need_erase_gran_bytes(const uint8_t *have, const uint8_t *want, unsigned int len, - unsigned int gran, const uint8_t erased_value) + unsigned int gran, const uint8_t erased_value) { unsigned int i, j, limit; for (j = 0; j < len / gran; j++) { @@ -816,14 +816,14 @@ * Warning: This function assumes that @have and @want point to naturally * aligned regions. * - * @have buffer with current content - * @want buffer with desired content + * @have buffer with current content + * @want buffer with desired content * @len length of the checked area * @gran write granularity (enum, not count) * @return 0 if no erase is needed, 1 otherwise */ int need_erase(const uint8_t *have, const uint8_t *want, unsigned int len, - enum write_granularity gran, const uint8_t erased_value) + enum write_granularity gran, const uint8_t erased_value) { int result = 0; unsigned int i; @@ -2323,8 +2323,8 @@ * @param buffer Target buffer to write image to. * @param buffer_len Size of target buffer in bytes. * @return 0 on success, - * 2 if buffer_len is too short for the flash chip's contents, - * or 1 on any other failure. + * 2 if buffer_len is too short for the flash chip's contents, + * or 1 on any other failure. */ int flashrom_image_read(struct flashctx *const flashctx, void *const buffer, const size_t buffer_len) { @@ -2380,13 +2380,13 @@ * @param buffer_len Size of source buffer in bytes. * @param refbuffer If given, assume flash chip contains same data as `refbuffer`. * @return 0 on success, - * 4 if buffer_len doesn't match the size of the flash chip, - * 3 if write was tried but nothing has changed, - * 2 if write failed and flash contents changed, - * or 1 on any other failure. + * 4 if buffer_len doesn't match the size of the flash chip, + * 3 if write was tried but nothing has changed, + * 2 if write failed and flash contents changed, + * or 1 on any other failure. */ int flashrom_image_write(struct flashctx *const flashctx, void *const buffer, const size_t buffer_len, - const void *const refbuffer) + const void *const refbuffer) { const size_t flash_size = flashctx->chip->total_size * 1024; const bool verify_all = flashctx->flags.verify_whole_chip; @@ -2521,9 +2521,9 @@ * @param buffer Source buffer to verify with. * @param buffer_len Size of source buffer in bytes. * @return 0 on success, - * 3 if the chip's contents don't match, - * 2 if buffer_len doesn't match the size of the flash chip, - * or 1 on any other failure. + * 3 if the chip's contents don't match, + * 2 if buffer_len doesn't match the size of the flash chip, + * or 1 on any other failure. */ int flashrom_image_verify(struct flashctx *const flashctx, const void *const buffer, const size_t buffer_len) { diff --git a/hwaccess.h b/hwaccess.h index af7054b..fb468b7 100644 --- a/hwaccess.h +++ b/hwaccess.h @@ -199,15 +199,15 @@ #include <machine/sysarch.h> #if defined(__NetBSD__) #if defined(__i386__) - #define iopl i386_iopl + #define iopl i386_iopl #elif defined(__x86_64__) - #define iopl x86_64_iopl + #define iopl x86_64_iopl #endif #elif defined (__OpenBSD__) #if defined(__i386__) - #define iopl i386_iopl + #define iopl i386_iopl #elif defined(__amd64__) - #define iopl amd64_iopl + #define iopl amd64_iopl #endif #endif
diff --git a/pickit2_spi.c b/pickit2_spi.c index a7c90a5..97741c8 100644 --- a/pickit2_spi.c +++ b/pickit2_spi.c @@ -60,39 +60,39 @@ static usb_dev_handle *pickit2_handle;
/* Default USB transaction timeout in ms */ -#define DFLT_TIMEOUT 10000 +#define DFLT_TIMEOUT 10000
-#define CMD_LENGTH 64 -#define ENDPOINT_OUT 0x01 -#define ENDPOINT_IN 0x81 +#define CMD_LENGTH 64 +#define ENDPOINT_OUT 0x01 +#define ENDPOINT_IN 0x81
-#define CMD_GET_VERSION 0x76 -#define CMD_SET_VDD 0xA0 -#define CMD_SET_VPP 0xA1 -#define CMD_READ_VDD_VPP 0xA3 -#define CMD_EXEC_SCRIPT 0xA6 -#define CMD_CLR_DLOAD_BUFF 0xA7 -#define CMD_DOWNLOAD_DATA 0xA8 -#define CMD_CLR_ULOAD_BUFF 0xA9 -#define CMD_UPLOAD_DATA 0xAA -#define CMD_END_OF_BUFFER 0xAD +#define CMD_GET_VERSION 0x76 +#define CMD_SET_VDD 0xA0 +#define CMD_SET_VPP 0xA1 +#define CMD_READ_VDD_VPP 0xA3 +#define CMD_EXEC_SCRIPT 0xA6 +#define CMD_CLR_DLOAD_BUFF 0xA7 +#define CMD_DOWNLOAD_DATA 0xA8 +#define CMD_CLR_ULOAD_BUFF 0xA9 +#define CMD_UPLOAD_DATA 0xAA +#define CMD_END_OF_BUFFER 0xAD
-#define SCR_SPI_READ_BUF 0xC5 -#define SCR_SPI_WRITE_BUF 0xC6 -#define SCR_SET_AUX 0xCF -#define SCR_LOOP 0xE9 -#define SCR_SET_ICSP_CLK_PERIOD 0xEA -#define SCR_SET_PINS 0xF3 -#define SCR_BUSY_LED_OFF 0xF4 -#define SCR_BUSY_LED_ON 0xF5 -#define SCR_MCLR_GND_OFF 0xF6 -#define SCR_MCLR_GND_ON 0xF7 -#define SCR_VPP_PWM_OFF 0xF8 -#define SCR_VPP_PWM_ON 0xF9 -#define SCR_VPP_OFF 0xFA -#define SCR_VPP_ON 0xFB -#define SCR_VDD_OFF 0xFE -#define SCR_VDD_ON 0xFF +#define SCR_SPI_READ_BUF 0xC5 +#define SCR_SPI_WRITE_BUF 0xC6 +#define SCR_SET_AUX 0xCF +#define SCR_LOOP 0xE9 +#define SCR_SET_ICSP_CLK_PERIOD 0xEA +#define SCR_SET_PINS 0xF3 +#define SCR_BUSY_LED_OFF 0xF4 +#define SCR_BUSY_LED_ON 0xF5 +#define SCR_MCLR_GND_OFF 0xF6 +#define SCR_MCLR_GND_ON 0xF7 +#define SCR_VPP_PWM_OFF 0xF8 +#define SCR_VPP_PWM_ON 0xF9 +#define SCR_VPP_OFF 0xFA +#define SCR_VPP_ON 0xFB +#define SCR_VDD_OFF 0xFE +#define SCR_VDD_ON 0xFF
/* Might be useful for other USB devices as well. static for now. * device parameter allows user to specify one device of multiple installed */
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Elyes HAOUAS (Code Review)