Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/47092 )
Change subject: chipset_enable.c: Add all the lakes support ......................................................................
chipset_enable.c: Add all the lakes support
Pulled out of ChromiumOS tree.
- pid=0x02a4 -> "Cometlake" - pid=0x34a4 -> "Icelake" - pid=0x4da4 -> "Jasperlake" - pid=0x51a4 -> "Alderlake-P" - pid=0x7aa4 -> "Alderlake-S" - pid=0x9d24 -> "Skylake" - pid=0x9da4 -> "Cannonlake" - pid=0xa0a4 -> "Tigerlake"
BUG=b:XXX BRANCH=none TEST=none
Change-Id: I403b11bbfc698e593fedd272921ade2bf8b3c2ca Signed-off-by: Edward O'Callaghan quasisec@google.com --- M chipset_enable.c 1 file changed, 10 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/92/47092/1
diff --git a/chipset_enable.c b/chipset_enable.c index 01d0291..3312483 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -1815,6 +1815,7 @@ {0x1166, 0x0200, B_P, OK, "Broadcom", "OSB4", enable_flash_osb4}, {0x1166, 0x0205, B_PFL, OK, "Broadcom", "HT-1000", enable_flash_ht1000}, {0x17f3, 0x6030, B_PFL, OK, "RDC", "R8610/R3210", enable_flash_rdc_r8610}, + {0x8086, 0x02a4, B_FS, OK, "Intel", "Cometlake", enable_flash_pch100}, {0x8086, 0x0c60, B_FS, NT, "Intel", "S12x0", enable_flash_s12x0}, {0x8086, 0x0f1c, B_FS, OK, "Intel", "Bay Trail", enable_flash_silvermont}, {0x8086, 0x0f1d, B_FS, NT, "Intel", "Bay Trail", enable_flash_silvermont}, @@ -1897,6 +1898,7 @@ {0x8086, 0x2918, B_FS, DEP, "Intel", "ICH9", enable_flash_ich9}, {0x8086, 0x2919, B_FS, DEP, "Intel", "ICH9M", enable_flash_ich9}, {0x8086, 0x31f0, B_FS, OK, "Intel", "Geminilake", enable_flash_apl}, + {0x8086, 0x34a4, B_FS, OK, "Intel", "Icelake", enable_flash_pch100}, {0x8086, 0x3a10, B_FS, NT, "Intel", "ICH10R Eng. Sample", enable_flash_ich10}, {0x8086, 0x3a14, B_FS, DEP, "Intel", "ICH10DO", enable_flash_ich10}, {0x8086, 0x3a16, B_FS, DEP, "Intel", "ICH10R", enable_flash_ich10}, @@ -1920,11 +1922,14 @@ {0x8086, 0x3b14, B_FS, DEP, "Intel", "3420", enable_flash_pch5}, {0x8086, 0x3b16, B_FS, NT, "Intel", "3450", enable_flash_pch5}, {0x8086, 0x3b1e, B_FS, NT, "Intel", "B55", enable_flash_pch5}, + {0x8086, 0x4da4, B_FS, OK, "Intel", "Jasperlake", enable_flash_pch100}, {0x8086, 0x5031, B_FS, OK, "Intel", "EP80579", enable_flash_ich7}, + {0x8086, 0x51a4, B_FS, OK, "Intel", "Alderlake-P", enable_flash_pch100}, {0x8086, 0x5af0, B_FS, OK, "Intel", "Apollolake", enable_flash_apl}, {0x8086, 0x7000, B_P, OK, "Intel", "PIIX3", enable_flash_piix4}, {0x8086, 0x7110, B_P, OK, "Intel", "PIIX4/4E/4M", enable_flash_piix4}, {0x8086, 0x7198, B_P, OK, "Intel", "440MX", enable_flash_piix4}, + {0x8086, 0x7aa4, B_FS, OK, "Intel", "Alderlake-S", enable_flash_pch100}, {0x8086, 0x8119, B_FL, OK, "Intel", "SCH Poulsbo", enable_flash_poulsbo}, {0x8086, 0x8186, B_FS, OK, "Intel", "Atom E6xx(T) (Tunnel Creek)", enable_flash_tunnelcreek}, {0x8086, 0x8c40, B_FS, NT, "Intel", "Lynx Point", enable_flash_pch8}, @@ -2008,6 +2013,7 @@ {0x8086, 0x9cc7, B_FS, NT, "Intel", "Broadwell Y Premium", enable_flash_pch9_lp}, {0x8086, 0x9cc9, B_FS, NT, "Intel", "Broadwell Y Base", enable_flash_pch9_lp}, {0x8086, 0x9ccb, B_FS, NT, "Intel", "Broadwell H", enable_flash_pch9}, + {0x8086, 0x9d24, B_FS, OK, "Intel", "Skylake", enable_flash_pch100}, {0x8086, 0x9d41, B_S, NT, "Intel", "Skylake / Kaby Lake Sample", enable_flash_pch100}, {0x8086, 0x9d43, B_S, NT, "Intel", "Skylake U Base", enable_flash_pch100}, {0x8086, 0x9d46, B_S, NT, "Intel", "Skylake Y Premium", enable_flash_pch100}, @@ -2020,7 +2026,9 @@ {0x8086, 0x9d56, B_S, NT, "Intel", "Kaby Lake Y Premium", enable_flash_pch100}, {0x8086, 0x9d58, B_S, NT, "Intel", "Kaby Lake U Premium", enable_flash_pch100}, {0x8086, 0x9d84, B_S, DEP, "Intel", "Cannon Lake U Premium", enable_flash_pch300}, + {0x8086, 0x9da4, B_FS, OK, "Intel", "Cannonlake", enable_flash_pch100}, {0x8086, 0x0284, B_S, DEP, "Intel", "Comet Lake U Premium", enable_flash_pch400}, + {0x8086, 0xa0a4, B_FS, OK, "Intel", "Tigerlake", enable_flash_pch100}, {0x8086, 0xa141, B_S, NT, "Intel", "Sunrise Point Desktop Sample", enable_flash_pch100}, {0x8086, 0xa142, B_S, NT, "Intel", "Sunrise Point Unknown Sample", enable_flash_pch100}, {0x8086, 0xa143, B_S, NT, "Intel", "H110", enable_flash_pch100}, @@ -2055,6 +2063,7 @@ {0x8086, 0xa1cb, B_S, NT, "Intel", "C621A Series Chipset (QS/PRQ)", enable_flash_c620}, {0x8086, 0xa1cc, B_S, NT, "Intel", "C627A Series Chipset (QS/PRQ)", enable_flash_c620}, {0x8086, 0xa1cd, B_S, NT, "Intel", "C629A Series Chipset (QS/PRQ)", enable_flash_c620}, + {0x8086, 0xa224, B_FS, OK, "Intel", "Lewisburg", enable_flash_pch100}, {0x8086, 0xa240, B_S, NT, "Intel", "C620 Series Chipset Supersku", enable_flash_c620}, {0x8086, 0xa241, B_S, NT, "Intel", "C620 Series Chipset Supersku", enable_flash_c620}, {0x8086, 0xa242, B_S, NT, "Intel", "C624 Series Chipset Supersku", enable_flash_c620}, @@ -2085,6 +2094,7 @@ {0x8086, 0xa30d, B_S, NT, "Intel", "HM370", enable_flash_pch300}, {0x8086, 0xa30e, B_S, DEP, "Intel", "CM246", enable_flash_pch300}, {0x8086, 0x3482, B_S, DEP, "Intel", "Ice Lake U Premium", enable_flash_pch300}, + {0x8086, 0xa0a4, B_FS, OK, "Intel", "Tigerlake", enable_flash_pch100}, #endif {0}, };
Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/47092 )
Change subject: chipset_enable.c: Add all the lakes support ......................................................................
Patch Set 1: Verified-1
-
Edward O'Callaghan (Code Review)