Nico Huber has submitted this change. ( https://review.coreboot.org/c/flashrom/+/55693 )
Change subject: Revert "ft2232_spi: Fix broken GPIOL cs_bits state (#126)" ......................................................................
Revert "ft2232_spi: Fix broken GPIOL cs_bits state (#126)"
This reverts commit a43e44b6abbe8381be3f3dd20a430973cf8b8ab5.
Nothing was broken. So this breaks everything. Well, actually only the `csgpiol` parameter. But that is very obvious.
`csgpiol` was added to use a GPIO pin as /CS. But this change impli- citly hardcoded /CS to ADBUS3.
Change-Id: I9ecdfe227585dda74658c16c96a57dd42d1d78b4 Signed-off-by: Nico Huber nico.h@gmx.de Reviewed-on: https://review.coreboot.org/c/flashrom/+/55693 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com Reviewed-by: Edward O'Callaghan quasisec@chromium.org --- M ft2232_spi.c 1 file changed, 1 insertion(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Edward O'Callaghan: Looks good to me, approved
diff --git a/ft2232_spi.c b/ft2232_spi.c index 78bf0fc..44975db 100644 --- a/ft2232_spi.c +++ b/ft2232_spi.c @@ -226,7 +226,7 @@
msg_pspew("Assert CS#\n"); buf[i++] = SET_BITS_LOW; - buf[i++] = ~ 0x08 & spi_data->cs_bits; /* assert CS (3rd) bit only */ + buf[i++] = 0 & ~spi_data->cs_bits; /* assertive */ buf[i++] = spi_data->pindir;
/* WREN, OP(PROGRAM, ERASE), ADDR, DATA */