[S] Change in flashrom[master]: chipset_enable.c: add PCI ID for TGL-UP3 SPI controller

[Jan Samek (Code Review)]

Jan Samek has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/70388 )

Change subject: chipset_enable.c: add PCI ID for TGL-UP3 SPI controller
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chipset_enable.c: add PCI ID for TGL-UP3 SPI controller

Add PCI ID for the Tiger Lake UP3 (Industrial SKU) SoC.

Change-Id: Ie93af14eb5857bfe51964f6565e475b6249dd407
Signed-off-by: Jan Samek 
---
M chipset_enable.c
1 file changed, 13 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/flashrom refs/changes/88/70388/1

diff --git a/chipset_enable.c b/chipset_enable.c
index b9144d1..ec1399f 100644
--- a/chipset_enable.c
+++ b/chipset_enable.c
@@ -2080,6 +2080,7 @@
    {0x8086, 0x0284, B_S,    DEP, "Intel", "Comet Lake U Premium",		enable_flash_pch400},
    {0x8086, 0x0285, B_S,    DEP, "Intel", "Comet Lake U Base",		enable_flash_pch400},
    {0x8086, 0xa082, B_S,    DEP, "Intel", "Tiger Lake U Premium",		enable_flash_pch500},
+	{0x8086, 0xa0a4, B_S,    DEP, "Intel", "Tiger Lake UP3",		enable_flash_pch500},
    {0x8086, 0xa141, B_S,    NT,  "Intel", "Sunrise Point Desktop Sample",	enable_flash_pch100},
    {0x8086, 0xa142, B_S,    NT,  "Intel", "Sunrise Point Unknown Sample",	enable_flash_pch100},
    {0x8086, 0xa143, B_S,    DEP, "Intel", "H110",				enable_flash_pch100},