[L] Change in flashrom[master]: ch347_spi.c: Add initial support for the WCH CH347

[Nicholas Chin (Code Review)]

Attention is currently required from: Thomas Heijligen, Angel Pons, qianfan, Anastasia Klimchuk, Nicholas Chin.

Hello build bot (Jenkins), Thomas Heijligen, Angel Pons, Anastasia Klimchuk,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/flashrom/+/70573

to look at the new patch set (#5).

Change subject: ch347_spi.c: Add initial support for the WCH CH347
......................................................................

ch347_spi.c: Add initial support for the WCH CH347

Add support for the WCH CH347, a high-speed USB to bus converter
supporting multiple protocols interfaces including SPI. Currently only
mode 1 (vendor defined communication interface) is supported, mode 2
(USB HID communication interface) support will be added later. The code
is currently hard coded to use a CS1 and a SPI clock of 60 MHz, though
there are 2 CS lines and 6 other GPIO lines available, as well as a
configurable clock divisor. Support for these will be exposed through
programmer parameters in later commits.

This currently uses the synchronous libusb API. Performance seems to be
alright so far, if it becomes an issue I may switch to the asynchronous
API.

Tested with a MX25L1606E flash chip and a hard coded divisor of 2 for a
SPI clock speed of 15 MHz, as I was having signal integrity issues at
higher clock speeds.

Signed-off-by: Nicholas Chin 
Change-Id: I31b86c41076cc45d4a416a73fa1131350fb745ba
---
M MAINTAINERS
M Makefile
A ch347_spi.c
M flashrom.8.tmpl
M include/programmer.h
M meson.build
M meson_options.txt
M programmer_table.c
M test_build.sh
9 files changed, 406 insertions(+), 9 deletions(-)

git pull ssh://review.coreboot.org:29418/flashrom refs/changes/73/70573/5