Attention is currently required from: Nico Huber, Caveh Jalali, Tim Wawrzynczak, Rizwan Qureshi, Edward O'Callaghan, Angel Pons, Nick Vaccaro, Alex Levin. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/61854 )
Change subject: ichspi.c: Check SPI Cycle In-Progress prior start HW Seq ......................................................................
Patch Set 2:
(3 comments)
Commit Message:
https://review.coreboot.org/c/flashrom/+/61854/comment/eb9c9ef3_248e7cbf PS1, Line 7: flashrom
nit: ichspi. […]
Ack
File ichspi.c:
https://review.coreboot.org/c/flashrom/+/61854/comment/879dad7a_9920fea0 PS1, Line 1390: REGREAD32
Isn't this register 16-bit?
Hardware Sequencing Flash Status and Control (BIOS_HSFSTS_CTL)—Offset 4h, 32 bit register
https://review.coreboot.org/c/flashrom/+/61854/comment/f5696c66_c8f57313 PS1, Line 1392: } while ((hsfsts & HSFS_SCIP) == HSFS_SCIP);
This loop could potentially never exit.
It depends on HW operation and here is what EDS says, so, I believe we might not run into such issue. Also, *Software must only program the next command when this bit is 0.*
SPI Cycle In Progress (H_SCIP): Hardware sets this bit when software sets the Flash Cycle Go (FGO) bit in the Hardware Sequencing Flash Control register. This bit remains set until the cycle completes on the SPI interface. Hardware automatically sets and clears this bit so that software can determine when read data is valid and/or when it is safe to begin programming the next command. Software must only program the next command when this bit is 0.