Change in flashrom[master]: ichspi.c: Check SPI Cycle In-Progress prior start HW Seq

[Edward O'Callaghan (Code Review)]

Attention is currently required from: Patrick Georgi, Stefan Reinauer, Angel Pons, Sridhar Siricilla, Alex Levin, YH Lin, Nico Huber, Martin Roth, Subrata Banik, Caveh Jalali, David Hendricks, Tim Wawrzynczak, Nick Vaccaro, Boris Mittelberg.
Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/61854 )

Change subject: ichspi.c: Check SPI Cycle In-Progress prior start HW Seq
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Patch Set 13:

(1 comment)

Commit Message:

https://review.coreboot.org/c/flashrom/+/61854/comment/2868861a_cfd68c9a 
PS7, Line 17: Without this synchronisation being implemented, flashrom is running
            : into below error:
            : 
            : Erasing and writing flash chip... Timeout error between offset
            : 0x0061c000 and 0x0061c03f (= 0x0061c000 + 63)! FAILED!
            : Uh oh. Erase/write failed. Checking if anything has changed.
> > > > > > Please let me know if anything we need to help for moving this CL? […]

ACK. This seems resolved based on my latest reading of the commit message.