Change in flashrom[staging]: fixup! flashrom: Add Skylake platform support

[Nico Huber (Code Review)]

Nico Huber has uploaded a new change for review. ( https://review.coreboot.org/18958 )

Change subject: fixup! flashrom: Add Skylake platform support
......................................................................

fixup! flashrom: Add Skylake platform support

Correctly abstract over PR0 register location

Change-Id: I91ef5ad2c055593bd40ecfc17dcd71b8ef27aeee
Signed-off-by: Nico Huber 
---
M ichspi.c
1 file changed, 17 insertions(+), 25 deletions(-)

git pull ssh://review.coreboot.org:29418/flashrom refs/changes/58/18958/1

diff --git a/ichspi.c b/ichspi.c
index e8fb74d..ed14338 100644
--- a/ichspi.c
+++ b/ichspi.c
@@ -70,7 +70,8 @@
 #define DLOCK_SSEQ_LOCKDN_OFF	16
 #define DLOCK_SSEQ_LOCKDN	(0x1 << DLOCK_SSEQ_LOCKDN_OFF)

-#define PCH100_REG_FPR0		0x84	/* 32 Bytes Protected Range 0 */
+#define PCH100_REG_FPR0		0x84	/* 32 Bits Protected Range 0 */
+#define PCH100_REG_GPR0		0x98	/* 32 Bits Global Protected Range 0 */

#define PCH100_REG_SSFSC	0xA0	/* 32 Bits Status (8) + Control (24) */
 #define PCH100_REG_PREOP	0xA4	/* 16 Bits */
@@ -1563,20 +1564,12 @@
    			 ((~((pr) >> PR_WP_OFF) & 1) << 1))

/* returns 0 if range is unused (i.e. r/w) */
-static int ich9_handle_pr(int i, int chipset)
+static int ich9_handle_pr(const size_t reg_pr0, int i)
 {
    static const char *const access_names[3] = {
    	"locked", "read-only", "write-only"
    };
-	uint8_t off;
-	switch (chipset) {
-	case CHIPSET_100_SERIES_SUNRISE_POINT:
-		off = PCH100_REG_FPR0 + (i * 4);
-		break;
-	default:
-		off = ICH9_REG_PR0 + (i * 4);
-		break;
-	}
+	uint8_t off = reg_pr0 + (i * 4);
    uint32_t pr = mmio_readl(ich_spibar + off);
    unsigned int rwperms = ICH_PR_PERMS(pr);

@@ -1593,17 +1586,9 @@

/* Set/Clear the read and write protection enable bits of PR register @i
  * according to @read_prot and @write_prot. */
-static void ich9_set_pr(int i, int read_prot, int write_prot, int chipset)
+static void ich9_set_pr(const size_t reg_pr0, int i, int read_prot, int write_prot)
 {
-	void *addr;
-	switch (chipset) {
-	case CHIPSET_100_SERIES_SUNRISE_POINT:
-		addr = ich_spibar + PCH100_REG_FPR0 + (i * 4);
-		break;
-	default:
-		addr = ich_spibar + ICH9_REG_PR0 + (i * 4);
-		break;
-	}
+	void *addr = ich_spibar + reg_pr0 + (i * 4);
    uint32_t old = mmio_readl(addr);
    uint32_t new;

@@ -1668,12 +1653,16 @@
    	ich_hwseq,
    	ich_swseq
    } ich_spi_mode = ich_auto;
+	size_t num_freg, num_pr, reg_pr0;

ich_generation = ich_gen;
    ich_spibar = spibar;

/* Moving registers / bits */
    if (ich_generation == CHIPSET_100_SERIES_SUNRISE_POINT) {
+		num_freg		= 6;
+		num_pr			= 6; /* PR5 is actually GPR0 */
+		reg_pr0			= PCH100_REG_FPR0;
    	swseq_data.reg_ssfsc	= PCH100_REG_SSFSC;
    	swseq_data.reg_preop	= PCH100_REG_PREOP;
    	swseq_data.reg_optype	= PCH100_REG_OPTYPE;
@@ -1682,6 +1671,9 @@
    	hwseq_data.only_4k	= true;
    	hwseq_data.hsfc_fcycle	= PCH100_HSFC_FCYCLE;
    } else {
+		num_freg		= 5;
+		num_pr			= 5;
+		reg_pr0			= ICH9_REG_PR0;
    	swseq_data.reg_ssfsc	= ICH9_REG_SSFS;
    	swseq_data.reg_preop	= ICH9_REG_PREOP;
    	swseq_data.reg_optype	= ICH9_REG_OPTYPE;
@@ -1805,7 +1797,7 @@
    		msg_pdbg("BRRA 0x%02x\n", ICH_BRRA(tmp));

/* Handle FREGx and FRAP registers */
-			for (i = 0; i < 5; i++)
+			for (i = 0; i < num_freg; i++)
    			ich_spi_rw_restricted |= ich9_handle_frap(tmp, i);
    		if (ich_spi_rw_restricted)
    			msg_pwarn("Not all flash regions are freely accessible by flashrom. This is "
@@ -1814,11 +1806,11 @@
    	}

/* Handle PR registers */
-		for (i = 0; i < 5; i++) {
+		for (i = 0; i < num_pr; i++) {
    		/* if not locked down try to disable PR locks first */
    		if (!ichspi_lock)
-				ich9_set_pr(i, 0, 0, ich_gen);
-			ich_spi_rw_restricted |= ich9_handle_pr(i, ich_gen);
+				ich9_set_pr(reg_pr0, i, 0, 0);
+			ich_spi_rw_restricted |= ich9_handle_pr(reg_pr0, i);
    	}

if (ich_spi_rw_restricted) {