Change in flashrom[master]: spi25_statusreg: inline spi_write_register_flag()

[Nikolai Artemiev (Code Review)]

Nikolai Artemiev has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/59528 )

Change subject: spi25_statusreg: inline spi_write_register_flag()
......................................................................

spi25_statusreg: inline spi_write_register_flag()

BUG=b:195381327,b:153800563
TEST=builds
BRANCH=none

Change-Id: I4996b0848d0ed09032bad2ab13ab1f40bbfc0304
Signed-off-by: Nikolai Artemiev 
---
M spi25_statusreg.c
1 file changed, 47 insertions(+), 61 deletions(-)

git pull ssh://review.coreboot.org:29418/flashrom refs/changes/28/59528/1

diff --git a/spi25_statusreg.c b/spi25_statusreg.c
index 61910ad..07d9d5a 100644
--- a/spi25_statusreg.c
+++ b/spi25_statusreg.c
@@ -21,58 +21,6 @@
 #include "chipdrivers.h"
 #include "spi.h"

-/* === Generic functions === */
-static int spi_write_register_flag(const struct flashctx *flash, uint8_t enable_opcode, uint8_t *write_cmd, size_t write_cmd_len)
-{
-	/*
-	 * Enabling register writes requires either EWSR or WREN depending on
-	 * chip type. The code below relies on the fact hat EWSR and WREN have
-	 * the same INSIZE and OUTSIZE.
-	 */
-
-	struct spi_command cmds[] = {
-	{
-		.writecnt	= JEDEC_WREN_OUTSIZE,
-		.writearr	= &enable_opcode,
-		.readcnt	= 0,
-		.readarr	= NULL,
-	}, {
-		.writecnt	= write_cmd_len,
-		.writearr	= write_cmd,
-		.readcnt	= 0,
-		.readarr	= NULL,
-	}, {
-		.writecnt	= 0,
-		.writearr	= NULL,
-		.readcnt	= 0,
-		.readarr	= NULL,
-	}};
-
-	int result = spi_send_multicommand(flash, cmds);
-	if (result) {
-		msg_cerr("%s failed during command execution\n", __func__);
-		/* No point in waiting for the command to complete if execution
-		 * failed.
-		 */
-		return result;
-	}
-	/* WRSR performs a self-timed erase before the changes take effect.
-	 * This may take 50-85 ms in most cases, and some chips apparently
-	 * allow running RDSR only once. Therefore pick an initial delay of
-	 * 100 ms, then wait in 10 ms steps until a total of 5 s have elapsed.
-	 */
-	int i = 0;
-	programmer_delay(100 * 1000);
-	while (spi_read_status_register(flash) & SPI_SR_WIP) {
-		if (++i > 490) {
-			msg_cerr("Error: WIP bit after WRSR never cleared\n");
-			return TIMEOUT_ERROR;
-		}
-		programmer_delay(10 * 1000);
-	}
-	return 0;
-}
-
 static const char *reg_name(enum flash_reg reg)
 {
    switch (reg) {
@@ -89,7 +37,6 @@

uint8_t write_cmd[3];
    size_t write_cmd_len = 0;
-	bool chip_supports_write = false;

/* Create SPI write command sequence based on the destination register
     * and the chip's supported command set. */
@@ -123,18 +70,57 @@
    	return 1;
    }

-	if (!(feature_bits & (FEATURE_WRSR_WREN | FEATURE_WRSR_EWSR))) {
+	uint8_t enable_cmd;
+	if (feature_bits & FEATURE_WRSR_WREN)
+		enable_cmd = JEDEC_WREN;
+	else if (feature_bits & FEATURE_WRSR_EWSR)
+		enable_cmd = JEDEC_EWSR;
+	else {
    	msg_cdbg("Missing status register write definition, assuming "
    		 "EWSR is needed\n");
-		feature_bits |= FEATURE_WRSR_EWSR;
+		enable_cmd = JEDEC_EWSR;
    }

-	int ret = 1;
-	if (feature_bits & FEATURE_WRSR_WREN)
-		ret = spi_write_register_flag(flash, JEDEC_WREN, write_cmd, write_cmd_len);
-	if (ret && (feature_bits & FEATURE_WRSR_EWSR))
-		ret = spi_write_register_flag(flash, JEDEC_EWSR, write_cmd, write_cmd_len);
-	return ret;
+	struct spi_command cmds[] = {
+	{
+		.writecnt	= JEDEC_WREN_OUTSIZE,
+		.writearr	= &enable_cmd,
+		.readcnt	= 0,
+		.readarr	= NULL,
+	}, {
+		.writecnt	= write_cmd_len,
+		.writearr	= write_cmd,
+		.readcnt	= 0,
+		.readarr	= NULL,
+	}, {
+		.writecnt	= 0,
+		.writearr	= NULL,
+		.readcnt	= 0,
+		.readarr	= NULL,
+	}};
+
+	int result = spi_send_multicommand(flash, cmds);
+	if (result) {
+		msg_cerr("%s failed during command execution\n", __func__);
+		return result;
+	}
+
+	/* WRSR performs a self-timed erase before the changes take effect.
+	 * This may take 50-85 ms in most cases, and some chips apparently
+	 * allow running RDSR only once. Therefore pick an initial delay of
+	 * 100 ms, then wait in 10 ms steps until a total of 5 s have elapsed.
+	 */
+	int i = 0;
+	programmer_delay(100 * 1000);
+	while (spi_read_status_register(flash) & SPI_SR_WIP) {
+		if (++i > 490) {
+			msg_cerr("Error: WIP bit after WRSR never cleared\n");
+			return TIMEOUT_ERROR;
+		}
+		programmer_delay(10 * 1000);
+	}
+	return 0;
+}
 }

int spi_read_register(const struct flashctx *flash, enum flash_reg reg, uint8_t *value)