Change in flashrom[master]: board_enable.c: Port to use pcidev_find_vendorclass() helper

[Edward O'Callaghan (Code Review)]

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/62405 )

Change subject: board_enable.c: Port to use pcidev_find_vendorclass() helper
......................................................................

board_enable.c: Port to use pcidev_find_vendorclass() helper

Change-Id: I3d8e3dbd5eeb057d7c959a82678cca2345fc69d9
Signed-off-by: Edward O'Callaghan 
---
M board_enable.c
1 file changed, 10 insertions(+), 16 deletions(-)

git pull ssh://review.coreboot.org:29418/flashrom refs/changes/05/62405/1

diff --git a/board_enable.c b/board_enable.c
index bc0c8ea..78c7f3c 100644
--- a/board_enable.c
+++ b/board_enable.c
@@ -1555,26 +1555,20 @@
    int i, allowed;

/* First, look for a known LPC bridge */
-	for (dev = pacc->devices; dev; dev = dev->next) {
-		uint16_t device_class;
-		/* libpci before version 2.2.4 does not store class info. */
-		device_class = pci_read_word(dev, PCI_CLASS_DEVICE);
-		if ((dev->vendor_id == 0x8086) &&
-		    (device_class == 0x0601)) { /* ISA bridge */
-			/* Is this device in our list? */
-			for (i = 0; intel_ich_gpio_table[i].id; i++)
-				if (dev->device_id == intel_ich_gpio_table[i].id)
-					break;
-
-			if (intel_ich_gpio_table[i].id)
-				break;
-		}
-	}
-
+	dev = pcidev_find_vendorclass(0x8086, 0x0601); /* ISA bridge */
    if (!dev) {
    	msg_perr("\nERROR: No known Intel LPC bridge found.\n");
    	return -1;
    }
+	/* Is this device in our list? */
+	for (i = 0; intel_ich_gpio_table[i].id; i++)
+		if (dev->device_id == intel_ich_gpio_table[i].id)
+			break;
+
+	if (!intel_ich_gpio_table[i].id) {
+		msg_perr("\nERROR: No known Intel LPC bridge found.\n");
+		return -1;
+	}

/*
     * According to the datasheets, all Intel ICHs have the GPIO bar 5:1