Change in flashrom[master]: Added support for GigaDevices GD25Q256C (4-byte addressing), Tested PREW

[David Hendricks (Code Review)]

David Hendricks has uploaded this change for review. ( https://review.coreboot.org/22824

Change subject: Added support for GigaDevices GD25Q256C (4-byte addressing), Tested PREW
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Added support for GigaDevices GD25Q256C (4-byte addressing), Tested PREW

Change-Id: Ie73de31748f767bae2455bd809209721d698803d
---
M flashchips.c
M flashchips.h
2 files changed, 48 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/flashrom refs/changes/24/22824/1

diff --git a/flashchips.c b/flashchips.c
index 77fcb90..4e6d350 100644
--- a/flashchips.c
+++ b/flashchips.c
@@ -6257,6 +6257,53 @@

{
    	.vendor		= "GigaDevice",
+		.name		= "GD25Q256C",
+		.bustype	= BUS_SPI,
+		.manufacture_id	= GIGADEVICE_ID,
+		.model_id	= GIGADEVICE_GD25Q256C,
+		.total_size	= 32768,
+		.page_size	= 256,
+		/* OTP: 768B total; read 0x48; write 0x42, erase 0x44 */
+		.feature_bits	= FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI | FEATURE_4BA_SUPPORT,
+		.four_bytes_addr_funcs =
+		{
+			.set_4ba = spi_enter_4ba_b7, /* enter 4-bytes addressing mode by CMD B7 */
+			.read_nbyte = spi_nbyte_read_4ba,  /* read from 4-bytes addressing mode */
+			.program_byte = spi_byte_program_4ba, /* write from 4-bytes addressing mode */
+			.program_nbyte = spi_nbyte_program_4ba /* write from 4-bytes addressing mode */
+		},
+		.tested		= TEST_OK_PREW,
+		.probe		= probe_spi_rdid,
+		.probe_timing	= TIMING_ZERO,
+		.block_erasers	=
+		{
+			{
+				.eraseblocks = { {4 * 1024, 8192} },
+				.block_erase = spi_block_erase_20_4ba,
+			}, {
+				.eraseblocks = { {32 * 1024, 1024} },
+				.block_erase = spi_block_erase_52_4ba,
+			}, {
+				.eraseblocks = { {64 * 1024, 512} },
+				.block_erase = spi_block_erase_d8_4ba,
+			}, {
+				.eraseblocks = { {32 * 1024 * 1024, 1} },
+				.block_erase = spi_block_erase_60,
+			}, {
+				.eraseblocks = { {32 * 1024 * 1024, 1} },
+				.block_erase = spi_block_erase_c7,
+			}
+		},
+		/* TODO: 2nd status reg (read 0x35, write 0x31) and 3rd status reg (read 0x15, write 0x11) */
+		.printlock	= spi_prettyprint_status_register_bp4_srwd,
+		.unlock		= spi_disable_blockprotect_bp4_srwd,
+		.write		= spi_chip_write_256,
+		.read		= spi_chip_read, /* Fast read (0x0B) and multi I/O supported */
+		.voltage	= {2700, 3600},
+	},
+
+	{
+		.vendor		= "GigaDevice",
    	.name		= "GD25T80",
    	.bustype	= BUS_SPI,
    	.manufacture_id	= GIGADEVICE_ID,
diff --git a/flashchips.h b/flashchips.h
index 6a7b0ae..46172fe 100644
--- a/flashchips.h
+++ b/flashchips.h
@@ -372,6 +372,7 @@
 #define GIGADEVICE_GD25Q32	0x4016	/* Same as GD25Q32B */
 #define GIGADEVICE_GD25Q64	0x4017	/* Same as GD25Q64B */
 #define GIGADEVICE_GD25Q128	0x4018	/* GD25Q128B and GD25Q128C only, can be distinguished by SFDP */
+#define GIGADEVICE_GD25Q256C	0x4019
 #define GIGADEVICE_GD25VQ21B	0x4212
 #define GIGADEVICE_GD25VQ41B	0x4213  /* Same as GD25VQ40C, can be distinguished by SFDP */
 #define GIGADEVICE_GD25VQ80C	0x4214