Attention is currently required from: Anne Macedo.
Anastasia Klimchuk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/76251?usp=email )
Change subject: flashchips: Add support for PUYA P25Q40H ......................................................................
Patch Set 1:
(5 comments)
Patchset:
PS1: Anne, thank you for your patch! I have few comments. If you have any questions, you are welcome to ask.
File flashchips.c:
https://review.coreboot.org/c/flashrom/+/76251/comment/378d4ce6_c0576523 : PS1, Line 13793: .manufacture_id = 0x85, : .model_id = 0x6013, These two ids should go to include/flashchips.h At the moment there is no section for Puya, so it needs to be added. There is a patch under review right now, which adds the Puya section and few ids (not the same, different chips), here is that patch CB:58134
I am not sure that original author of CB:58134 will return back, so it could be me finishing that patch. So maybe you can add Puya section and your ids into include/flashchips.h (using CB:58134 as example), and then I can rebase CB:58134 on the top of your patch.
https://review.coreboot.org/c/flashrom/+/76251/comment/0c7d3b58_bcf5bb8a : PS1, Line 13797: .feature_bits = FEATURE_WRSR_WREN, It also supports FEATURE_OTP
https://review.coreboot.org/c/flashrom/+/76251/comment/55426530_fa3b36aa : PS1, Line 13813: .eraseblocks = { {512 * 1024, 1} }, : .block_erase = SPI_BLOCK_ERASE_81, Command 81 is doing page erase for 256 bytes. This is the smallest eraseblock, should be the first (the current definition sets this as if it is full chip erase, which is not).
And, there is a chip erase in the datasheet, command 60 or C7, these two should come last in the list.
https://review.coreboot.org/c/flashrom/+/76251/comment/5d93e54b_d87aced9 : PS1, Line 13817: SPI_PRETTYPRINT_STATUS_REGISTER_BP3_SRWD I think this should be BP4, and same for the unlock