[M] Change in flashrom[main]: ch347_spi: Fix CH347T PID, interface, and clock settings errors

[ZhiYuanNJ (Code Review)]

Attention is currently required from: Nicholas Chin.

ZhiYuanNJ has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/82193?usp=email )

Change subject: ch347_spi: Fix CH347T PID, interface, and clock settings errors
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Patch Set 4:

(13 comments)

Commit Message:

https://review.coreboot.org/c/flashrom/+/82193/comment/67c31ce5_f0f8db70 :
PS2, Line 7: Bug fix: Fix CH347T PID, interface, and clock settings errors
> The typical commit message style is `<component>: Short description (up to 72 characters)` (see http […]

Done

https://review.coreboot.org/c/flashrom/+/82193/comment/f52a18e7_811f32e0 :
PS2, Line 10: The latest package with F as 347, compared to T, does not require active mode switching and can simultaneously meet communication requirements such as USB to SPI/I2C
> Please reflow to 72 characters per line

Done

https://review.coreboot.org/c/flashrom/+/82193/comment/3f0781e7_f90e257e :
PS2, Line 10: The latest package with F as 347, compared to T, does not require active mode switching and can simultaneously meet communication requirements such as USB to SPI/I2C
> Please reflow to 72 characters per line

Done

https://review.coreboot.org/c/flashrom/+/82193/comment/839a99e2_9f45ebf0 :
PS2, Line 12: ?from=search&wd=eyJpdiI6Im4zdVRJdHdpNks1WUFLSUFDNnRsYnc9PSIsInZhbHVlIjoicHFsU3EwQlgzWmgzM1ZIYnBpZXFiUT09IiwibWFjIjoiNjZjNjc5ZDQ4Yzg2ZDdhNzc5YzM4OTA0MTlkM2FiYWQ1Yzg0ZTZkNWNiZDczZDM1NjM1ODIwN2NjZDhlOTNmOCJ9
> Everything from the `?` onwards isn't necessary to navigate to the product page

Done

https://review.coreboot.org/c/flashrom/+/82193/comment/d28deb28_ee982ff6 :
PS2, Line 12: ?from=search&wd=eyJpdiI6Im4zdVRJdHdpNks1WUFLSUFDNnRsYnc9PSIsInZhbHVlIjoicHFsU3EwQlgzWmgzM1ZIYnBpZXFiUT09IiwibWFjIjoiNjZjNjc5ZDQ4Yzg2ZDdhNzc5YzM4OTA0MTlkM2FiYWQ1Yzg0ZTZkNWNiZDczZDM1NjM1ODIwN2NjZDhlOTNmOCJ9
> Everything from the `?` onwards isn't necessary to navigate to the product page

Done

File ch347_spi.c:

PS2:
> I would split the spispeed changes into a separate patch so that this one is just about adding the C […]

Do I need to open a separate submission for the issue of device speed settings in this submission?

PS2:
> Please use the `/* comment */` comment style rather than `//coment` for consistency with the rest of […]

Done

https://review.coreboot.org/c/flashrom/+/82193/comment/0f24d584_716d43e1 :
PS2, Line 10: *                                                                         
            :  *   CH347 is a high-speed USB bus converter chip that provides UART, I2C  
            :  *   and SPI synchronous serial ports and JTAG interface through USB bus.  
            :  *                                                                         
            :  *   The SPI interface by CH347 can supports transmission frequency       
            :  *   configuration up to 60MHz.                                            
            :  *                                                                         
            :  *   The USB2.0 to spi scheme based on CH347 can be used to build         
            :  *   customized USB high-speed spi debugger and other products.           
            :  *                                                                         
            :  *            _____________                                                
            :  *           |             |____SPI (MISO,MOSI,SCK,CSC0,CSC1)            
            :  *      USB__|   CH347T/F  |                                               
            :  *           |_____________|____(UART/I2C/JTAG/SWD/GPIO)             
            :  *            ______|______                                                
            :  *           |             |                                               
            :  *           | 8 MHz XTAL  |                                               
            :  *           |_____________|     
            :  *
> This should be placed after the licence header, not in the middle of it. […]

Done

https://review.coreboot.org/c/flashrom/+/82193/comment/bf99344c_d7c39384 :
PS2, Line 79: 0x55DD
> This should be left at 0x55DB, which corresponds to mode 1. […]

Thank you for the reminder, Corrected.

https://review.coreboot.org/c/flashrom/+/82193/comment/f8ba5ba6_63cbd15e :
PS2, Line 97: 2,       //CH347T interface number
            : 	4,       //CH347F interface number
> Use the `CH347*_IFACE` defines from above? That also removes the need for the comments

Done

https://review.coreboot.org/c/flashrom/+/82193/comment/746e374c_59713052 :
PS2, Line 344: Couldn't open device %04x:%04x.\n
> This block of code would only run if flashrom has gone through all the IDs in `devs_ch347_spi` and w […]

Done

https://review.coreboot.org/c/flashrom/+/82193/comment/e1d9326d_fb4eea64 :
PS2, Line 347:
> Remove trailing whiespace

Done

https://review.coreboot.org/c/flashrom/+/82193/comment/00c2db12_1d74593c :
PS2, Line 356: Failed to claim interface 2
> Update this to reflect the actual interface number being used

Done