Change in flashrom[staging]: spi: Add valid_addr_offset() to spi_master

[Nico Huber (Code Review)]

Nico Huber has uploaded a new change for review. ( https://review.coreboot.org/19418 )

Change subject: spi: Add valid_addr_offset() to spi_master
......................................................................

spi: Add valid_addr_offset() to spi_master

Get rid of the layering violations around ICH's BBAR.

Change-Id: Icbac513c5339e8aff624870252133284ef85ab73
Signed-off-by: Nico Huber 
---
M ichspi.c
M programmer.h
M spi.c
3 files changed, 20 insertions(+), 11 deletions(-)

git pull ssh://review.coreboot.org:29418/flashrom refs/changes/18/19418/1

diff --git a/ichspi.c b/ichspi.c
index e1395ee..1ab114c 100644
--- a/ichspi.c
+++ b/ichspi.c
@@ -639,6 +639,17 @@
    		 min_addr, ichspi_bbar);
 }

+static uint32_t ich_valid_addr_offset(struct flashctx *const flash)
+{
+	switch (ich_generation) {
+	case CHIPSET_ICH7:
+	case CHIPSET_ICH9:
+		return ichspi_bbar;
+	default:
+		return 0;
+	}
+}
+
 /* Read len bytes from the fdata/spid register into the data array.
  *
  * Note that using len > flash->mst->spi.max_data_read will return garbage or
@@ -1539,6 +1550,7 @@
    .read = default_spi_read,
    .write_256 = default_spi_write_256,
    .write_aai = default_spi_write_aai,
+	.valid_addr_offset = ich_valid_addr_offset,
 };

static const struct spi_master spi_master_ich9 = {
@@ -1550,6 +1562,7 @@
    .read = default_spi_read,
    .write_256 = default_spi_write_256,
    .write_aai = default_spi_write_aai,
+	.valid_addr_offset = ich_valid_addr_offset,
 };

static const struct opaque_master opaque_master_ich_hwseq = {
diff --git a/programmer.h b/programmer.h
index 63057d7..b5306db 100644
--- a/programmer.h
+++ b/programmer.h
@@ -595,6 +595,10 @@
    int (*write_256)(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len);
    int (*write_aai)(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len);
    const void *data;
+
+	/* Get the lowest allowed address for flash accesses.
+	   If not set, a constant zero offset will be assumed. */
+	uint32_t (*valid_addr_offset)(struct flashctx *flash);
 };

int default_spi_send_command(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt,
diff --git a/spi.c b/spi.c
index 894f73f..4e50fc1 100644
--- a/spi.c
+++ b/spi.c
@@ -146,18 +146,10 @@
  */
 uint32_t spi_get_valid_read_addr(struct flashctx *flash)
 {
-	switch (flash->mst->spi.type) {
-#if CONFIG_INTERNAL == 1
-#if defined(__i386__) || defined(__x86_64__)
-	case SPI_CONTROLLER_ICH7:
-	case SPI_CONTROLLER_ICH9:
-		/* Return BBAR for ICH chipsets. */
-		return ichspi_bbar;
-#endif
-#endif
-	default:
+	if (flash->mst->spi.valid_addr_offset)
+		return flash->mst->spi.valid_addr_offset(flash);
+	else
    	return 0;
-	}
 }

int spi_aai_write(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len)