Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/78142?usp=email )
Change subject: flashchips: Add write-protect support for MXIC MX25U25643G ......................................................................
flashchips: Add write-protect support for MXIC MX25U25643G
The MX25U25643G has a WPSEL bit in the security register, but the MX25U25635F does not. Therefore, take them apart.
We have tested --wp-enable, --wp-disable, --wp-list and --wp-range commands for write-protect feature.
The MX25U25643G has been tested by ch341a programmer : read, write, erase and wp.
MX25U25643G datasheet is available at the following URL: https://www.mxic.com.tw/en-us/products/NOR-Flash/Serial-NOR-Flash/Pages/spec...
MX25U25635F datasheet is available at the following URL: https://www.macronix.com/en-us/products/NOR-Flash/Serial-NOR-Flash/Pages/spe...
Change-Id: I43de9ed123b9736c04d070754bcf9c32be5697ad Signed-off-by: rogeryou rogeryou@mxic.com.cn Reviewed-on: https://review.coreboot.org/c/flashrom/+/78142 Reviewed-by: Anastasia Klimchuk aklm@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M flashchips.c 1 file changed, 58 insertions(+), 1 deletion(-)
Approvals: Anastasia Klimchuk: Looks good to me, approved build bot (Jenkins): Verified
diff --git a/flashchips.c b/flashchips.c index db20cba..e156ffb 100644 --- a/flashchips.c +++ b/flashchips.c @@ -10207,7 +10207,7 @@
{ .vendor = "Macronix", - .name = "MX25U25635F/MX25U25643G", + .name = "MX25U25635F", .bustype = BUS_SPI, .manufacture_id = MACRONIX_ID, .model_id = MACRONIX_MX25U25635F, @@ -10256,6 +10256,63 @@
{ .vendor = "Macronix", + .name = "MX25U25643G", + .bustype = BUS_SPI, + .manufacture_id = MACRONIX_ID, + .model_id = MACRONIX_MX25U25635F, + .total_size = 32768, + .page_size = 256, + /* OTP: 512B total; enter 0xB1, exit 0xC1 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI | FEATURE_4BA | FEATURE_CFGR | FEATURE_SCUR, + .tested = TEST_OK_PREWB, + .probe = PROBE_SPI_RDID, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 8192} }, + .block_erase = SPI_BLOCK_ERASE_21, + }, { + .eraseblocks = { {4 * 1024, 8192} }, + .block_erase = SPI_BLOCK_ERASE_20, + }, { + .eraseblocks = { {32 * 1024, 1024} }, + .block_erase = SPI_BLOCK_ERASE_5C, + }, { + .eraseblocks = { {32 * 1024, 1024} }, + .block_erase = SPI_BLOCK_ERASE_52, + }, { + .eraseblocks = { {64 * 1024, 512} }, + .block_erase = SPI_BLOCK_ERASE_DC, + }, { + .eraseblocks = { {64 * 1024, 512} }, + .block_erase = SPI_BLOCK_ERASE_D8, + }, { + .eraseblocks = { {32 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_60, + }, { + .eraseblocks = { {32 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_C7, + } + }, + /* TODO: security register */ + .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP3_SRWD, /* bit6 is quad enable */ + .unlock = SPI_DISABLE_BLOCKPROTECT_BP3_SRWD, + .write = SPI_CHIP_WRITE256, /* Multi I/O supported */ + .read = SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {1650, 2000}, + .reg_bits = + { + .srp = {STATUS1, 7, RW}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 5, RW}}, + .tb = {CONFIG, 3, OTP}, + .wps = {SECURITY, 7, OTP}, /* This bit is set by WPSEL command */ + }, + .decode_range = DECODE_RANGE_SPI25, + }, + + { + .vendor = "Macronix", .name = "MX25U3235E/F", .bustype = BUS_SPI, .manufacture_id = MACRONIX_ID,