[S] Change in flashrom[main]: how_to_add_new_chip: Add a section for feature bits and WRSR handling

[Anastasia Klimchuk (Code Review)]

Attention is currently required from: Hsuan Ting Chen, Hsuan-ting Chen, Thomas Heijligen.

Anastasia Klimchuk has posted comments on this change by Hsuan-ting Chen. ( https://review.coreboot.org/c/flashrom/+/82908?usp=email )

Change subject: how_to_add_new_chip: Add a section for feature bits and WRSR handling
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Patch Set 1:

(5 comments)

File doc/contrib_howtos/how_to_add_new_chip.rst:

https://review.coreboot.org/c/flashrom/+/82908/comment/7f6a0db4_04132885?usp... :
PS1, Line 120: This
Delete "This", start with "Indicates that"

https://review.coreboot.org/c/flashrom/+/82908/comment/ef389f53_43080cbc?usp... :
PS1, Line 124: This
same

https://review.coreboot.org/c/flashrom/+/82908/comment/45eb2bae_f380d8b3?usp... :
PS1, Line 125: priort
typo, prior

https://review.coreboot.org/c/flashrom/+/82908/comment/9268e6e7_9f208fca?usp... :
PS1, Line 110: 
             : Write-Status-Register (WRSR) Handling
             : ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
             : 
             : ``FEATURE_WRSR_EWSR``, ``FEATURE_WRSR_WREN``, and ``FEATURE_WRSR_EITHER``. These bits used for **SPI only**.
             : 
             : The Write Status Register (WRSR) is used to configure various settings within the flash chip, including write protection and
             : other features. The way WRSR is accessed varies between SPI flash chips, leading to the need for these feature bits.
             : 
             : * ``FEATURE_WRSR_EWSR``:
             :   This indicates that we need an **Enable-Write-Status-Register** (EWSR) instruction which opens the status register for the
             :   immediately-followed next WRSR instruction. Usually, the opcode is **0x50**.
             : 
             : * ``FEATURE_WRSR_WREN``:
             :   This indicates that we need an **Write-Enable** (WREN) instruction to set the Write Enable Latch (WEL) bit. The WEL bit
             :   must be set priort to every WRSR command. Usually, the opcode is **0x06**.
             : 
             : * ``FEATURE_WRSR_EITHER``:
             :   This indicates that either EWSR or WREN is supported in this chip.
Maybe move this section to "Write-protection" , below? You can skip the intro, and rename the section as "Feature bits for Write-Status-Register (WRSR) Handling".

You mentioned you have further plans to update the doc, maybe you can tell me the plan? Then we can come up with a doc structure which aligns with you next plans!

https://review.coreboot.org/c/flashrom/+/82908/comment/96f001fb_342587b0?usp... :
PS1, Line 128: This
same