Attention is currently required from: Edward O'Callaghan.
Sam McNally has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/71576 )
Change subject: chipset_enable.c: Add TL UP3 and UP4/Y id's ......................................................................
Patch Set 1:
(2 comments)
File chipset_enable.c:
https://review.coreboot.org/c/flashrom/+/71576/comment/339e3db0_c567540c PS1, Line 2083: {0x8086, 0xa083, B_S, DEP, "Intel", "Tiger Lake U Premium 3", enable_flash_pch500}, As far as I can tell, 0xa083 isn't used after all, so we don't need to add this.
https://review.coreboot.org/c/flashrom/+/71576/comment/d1f3ec48_db6bf680 PS1, Line 2084: U Premium 4/Y If we follow the final naming scheme this should be "Tiger Lake Premium UP4". If we follow earlier platforms, and the coreboot scheme, then "Tiger Lake Y Premium".
-
Sam McNally (Code Review)