Attention is currently required from: Angel Pons, Nicholas Chin.
qianfan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/70529 )
Change subject: Add initial CH347T SPI programmer ......................................................................
Patch Set 7:
(5 comments)
Commit Message:
PS3:
It would probably be good to specify that this only supports mode 1 (vendor protocol) right now and […]
Done
File ch347t_spi.c:
https://review.coreboot.org/c/flashrom/+/70529/comment/10ccaa0f_5d1328a7 PS3, Line 179: buf, n + 3,
Let's use the default value as same as DLL. […]
Done
File ch347t_spi.c:
https://review.coreboot.org/c/flashrom/+/70529/comment/22b26131_bb8b720c PS5, Line 94: typedef uint32_t __le32;
all the data structure transfed to ch347 should be little endian. […]
Done
https://review.coreboot.org/c/flashrom/+/70529/comment/b01fd317_7e0e1eb5 PS5, Line 110: } __attribute__((packed));
It's not just about the attribute, but the effects of struct packing. […]
Hi, I had changed the ch347_spi_cs_param structure, please review again.
https://review.coreboot.org/c/flashrom/+/70529/comment/16209413_95d07cbe PS5, Line 169: if (n > CH347_MAX_DATA_WRITE) : n = CH347_MAX_DATA_WRITE;
Yes, I believe this code is for splitting up transfers into smaller transfers. […]
Done
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qianfan (Code Review)