[S] Change in flashrom[main]: flashchips/winbond.c: Add reg_bits for W25Q256JW

[Anastasia Klimchuk (Code Review)]

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/85323?usp=email )

Change subject: flashchips/winbond.c: Add reg_bits for W25Q256JW
......................................................................

flashchips/winbond.c: Add reg_bits for W25Q256JW

Add reg_bits for W25Q256JW as per the datasheet. The register
definitions are same as W25Q256JW_DTR.

Datasheet: https://www.winbond.com/hq/support/documentation/levelOne.jsp?__locale=en&am...

BUG=b:376929528
TEST=Program and verify WP ranges

```
flashrom -p internal --wp-status
flashrom -p internal --wp-range 0x0,0x2000000
flashrom -p internal --wp-enable
flashrom -p internal --wp-status
```

Change-Id: I050754b28a90911a50f891869297524ce9a6720e
Signed-off-by: Kapil Porwal 
Reviewed-on: https://review.coreboot.org/c/flashrom/+/85323
Tested-by: build bot (Jenkins) 
Reviewed-by: Anastasia Klimchuk 
Reviewed-by: Subrata Banik 
---
M flashchips/winbond.c
1 file changed, 13 insertions(+), 2 deletions(-)

Approvals:
  Subrata Banik: Looks good to me, but someone else must approve
  Anastasia Klimchuk: Looks good to me, approved
  build bot (Jenkins): Verified

diff --git a/flashchips/winbond.c b/flashchips/winbond.c
index 973bf2c..9709e78 100644
--- a/flashchips/winbond.c
+++ b/flashchips/winbond.c
@@ -655,8 +655,9 @@
    	.page_size	= 256,
    	/* supports SFDP */
    	/* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44, read ID 0x4B */
-		.feature_bits	= FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA,
-		.tested		= TEST_OK_PREW,
+		.feature_bits	= FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA | FEATURE_WRSR2
+				  | FEATURE_WRSR3,
+		.tested		= TEST_OK_PREWB,
    	.probe		= PROBE_SPI_RDID,
    	.probe_timing	= TIMING_ZERO,
    	.block_erasers	=
@@ -689,6 +690,16 @@
    	.write		= SPI_CHIP_WRITE256,
    	.read		= SPI_CHIP_READ,
    	.voltage	= {1650, 1950},
+		.reg_bits	=
+		{
+			.srp	= {STATUS1, 7, RW},
+			.srl	= {STATUS2, 0, RW},
+			.bp	= {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 5, RW}},
+			.tb	= {STATUS1, 6, RW},
+			.cmp	= {STATUS2, 6, RW},
+			.wps	= {STATUS3, 2, RW},
+		},
+		.decode_range	= DECODE_RANGE_SPI25,
    },

{