Hello Carl-Daniel Hailfinger,
I'd like you to do a code review. Please visit
to review the following change.
Change subject: Fix another SB600 SPI corner case ......................................................................
Fix another SB600 SPI corner case
SB600 SPI has an off-by-one error during read, and that hardware issue is not documented anywhere yet. r661 tried to work around this, but the fix had unpleasant side effects. The new workaround only triggers if readcnt is nonzero, eliminating all possible interactions with write-only commands.
Change-Id: I72a3725449652773ca1d6df18ee76901d617b74c Signed-off-by: Carl-Daniel Hailfinger email@example.com --- M sb600spi.c 1 file changed, 6 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/51/23051/1
diff --git a/sb600spi.c b/sb600spi.c index 68f8d8a..a5499ff 100644 --- a/sb600spi.c +++ b/sb600spi.c @@ -245,9 +245,13 @@ * an opcode and no additional data/address, the SPI controller will * read one byte too few from the chip. Basically, the last byte of * the chip response is discarded and will not end up in the FIFO. - * It is unclear if the CS# line is set high too early as well. + * It is unclear if the CS# line is set high too early as well, but + * it seems CS# line timing matches the bytecounts we specify, so there + * is a mismatch between FIFO content count and CS# timing. + * Only trigger this if readcnt is nonzero on the assumption that + * reading more doesn't hurt if we already read soemthing. */ - unsigned int readoffby1 = (writecnt > 0) ? 0 : 1; + unsigned int readoffby1 = (writecnt == 0 && readcnt > 0) ? 1 : 0; uint8_t readwrite = (readcnt + readoffby1) << 4 | (writecnt); mmio_writeb(readwrite, sb600_spibar + 1);