[M] Change in flashrom[main]: flashchips: add GD25LF256F

[Anastasia Klimchuk (Code Review)]

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/83717?usp=email )

Change subject: flashchips: add GD25LF256F
......................................................................

flashchips: add GD25LF256F

added GD25LF256F on flashchips.c
added GIGADEVICE_GD25LF256F=0x6319 on flashchip.h

GD25LF256F is a higher performance 1.8V 256Mbit SPI flash

I have tested on CH347 with erase, program, read, protection.

Change-Id: I21a71606476e823faa38a7920aa2b10e25d68d26
Signed-off-by: Victor 
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83717
Tested-by: build bot (Jenkins) 
Reviewed-by: Anastasia Klimchuk 
---
M flashchips.c
M include/flashchips.h
2 files changed, 59 insertions(+), 1 deletion(-)

Approvals:
  Anastasia Klimchuk: Looks good to me, approved
  build bot (Jenkins): Verified

diff --git a/flashchips.c b/flashchips.c
index 01cf641..60fbb1b 100644
--- a/flashchips.c
+++ b/flashchips.c
@@ -6585,7 +6585,64 @@
    	.decode_range	= DECODE_RANGE_SPI25,
    },

-        {
+	{
+		.vendor		= "GigaDevice",
+		.name		= "GD25LF256F",
+		.bustype	= BUS_SPI,
+		.manufacture_id	= GIGADEVICE_ID,
+		.model_id	= GIGADEVICE_GD25LF256F,
+		.total_size	= 32768,
+		.page_size	= 256,
+		/* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44 */
+		.feature_bits	= FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_WRSR_EXT2 | FEATURE_4BA,
+		.tested		= TEST_OK_PREWB,
+		.probe		= PROBE_SPI_RDID,
+		.probe_timing	= TIMING_ZERO,
+		.block_erasers	=
+		{
+			{
+				.eraseblocks = { {4 * 1024, 8192} },
+				.block_erase = SPI_BLOCK_ERASE_21,
+			}, {
+				.eraseblocks = { {4 * 1024, 8192} },
+				.block_erase = SPI_BLOCK_ERASE_20,
+			}, {
+				.eraseblocks = { {32 * 1024, 1024} },
+				.block_erase = SPI_BLOCK_ERASE_5C,
+			}, {
+				.eraseblocks = { {32 * 1024, 1024} },
+				.block_erase = SPI_BLOCK_ERASE_52,
+			}, {
+				.eraseblocks = { {64 * 1024, 512} },
+				.block_erase = SPI_BLOCK_ERASE_DC,
+			}, {
+				.eraseblocks = { {64 * 1024, 512} },
+				.block_erase = SPI_BLOCK_ERASE_D8,
+			}, {
+				.eraseblocks = { {32 * 1024 * 1024, 1} },
+				.block_erase = SPI_BLOCK_ERASE_60,
+			}, {
+				.eraseblocks = { {32 * 1024 * 1024, 1} },
+				.block_erase = SPI_BLOCK_ERASE_C7,
+			}
+		},
+		.printlock	= SPI_PRETTYPRINT_STATUS_REGISTER_BP4_SRWD,
+		.unlock		= SPI_DISABLE_BLOCKPROTECT_BP4_SRWD, /* TODO: 2nd status reg (read with 0x35) */
+		.write		= SPI_CHIP_WRITE256,
+		.read		= SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */
+		.voltage	= {1650, 2000},
+		.reg_bits	=
+		{
+			.srp    = {STATUS1, 7, RW},
+			.srl    = {STATUS2, 0, RW},
+			.bp     = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 5, RW}},
+			.tb    = {STATUS1, 6, RW}, /* Called BP4 in datasheet, acts like TB */
+			.cmp    = {STATUS2, 6, RW},
+		},
+		.decode_range	= DECODE_RANGE_SPI25,
+	},
+
+	{
    	.vendor		= "GigaDevice",
    	.name		= "GD25LQ128E/GD25LB128E/GD25LR128E/GD25LQ128D/GD25LQ128C",
    	.bustype	= BUS_SPI,
diff --git a/include/flashchips.h b/include/flashchips.h
index c4b13d9..d8146ec 100644
--- a/include/flashchips.h
+++ b/include/flashchips.h
@@ -405,6 +405,7 @@
 #define GIGADEVICE_GD25LQ128CD	0x6018
 #define GIGADEVICE_GD25LQ255E	0x6019
 #define GIGADEVICE_GD25LF128E	0x6318
+#define GIGADEVICE_GD25LF256F	0x6319
 #define GIGADEVICE_GD25LR256E	0x6719
 #define GIGADEVICE_GD25LR512ME	0x671A
 #define GIGADEVICE_GD25WQ80E	0x6514