Change in flashrom[staging]: WIP: ich_descriptors: Update for Intel Skylake

[Nico Huber (Code Review)]

Nico Huber has uploaded a new change for review. ( https://review.coreboot.org/18973 )

Change subject: WIP: ich_descriptors: Update for Intel Skylake
......................................................................

WIP: ich_descriptors: Update for Intel Skylake

Change-Id: Idd60a857d1ecffcb2e437af21134d9de44dcceb8
Signed-off-by: Nico Huber 
---
M ich_descriptors.h
1 file changed, 95 insertions(+), 92 deletions(-)

git pull ssh://review.coreboot.org:29418/flashrom refs/changes/73/18973/1

diff --git a/ich_descriptors.h b/ich_descriptors.h
index df4dd76..ab4af1e 100644
--- a/ich_descriptors.h
+++ b/ich_descriptors.h
@@ -77,7 +77,7 @@
    			 NC	:2, /* Number Of Components */
    				:6,
    			 FRBA	:8, /* Flash Region Base Address */
-				 NR	:3, /* Number Of Regions */
+				 NR	:3, /* Number Of Regions (reserved from Skylake on) */
    				:5;
    	};
    };
@@ -94,9 +94,10 @@
    union {			/* 0x0c */
    	uint32_t FLMAP2;
    	struct {
-			uint32_t FMSBA	:8, /* Flash (G)MCH Strap Base Addr. */
-				 MSL	:8, /* MCH Strap Length */
-					:16;
+			uint32_t FMSBA		:8, /* Flash (G)MCH Strap Base Addr. */
+				 MSL		:8, /* MCH Strap Length */
+				 ICCRIBA	:8, /* ICC Reg. Init Base Addr.	(new since Sandy Bridge) */
+				 RIL		:8; /* Register Init Length	(new since Hawell) */
    	};
    };
 };
@@ -116,7 +117,8 @@
    	 * Patsburg:		50		30		5	0:2, 3:5
    	 * Panther Point/7	50		30		5	0:2, 3:5
    	 * Lynx Point/8:	50		30		7	0:3, 4:7
-		 * Wildcat Point/9:	50		?? (multi I/O)	?	?:?, ?:?
+		 * Wildcat Point/9:	50		?? (multi I/O)	7	?:?, ?:?
+		 * Sunrise Point/100:	48		??		7	0:3, 4:7
    	 */
    	struct {
    		uint32_t		:17,
@@ -149,106 +151,107 @@
    	};
    };
    union {			/* 0x08 */
-		uint32_t FLPB; /* Flash Partition Boundary Register */
+		uint32_t FLPB; /* Flash Partition Boundary Register, until Panther Point/7 */
    	struct {
    		uint32_t FPBA	:13, /* Flash Partition Boundary Addr */
    				:19;
    	};
-	};
-};
-
-struct ich_desc_region {
-	union {
-		uint32_t FLREGs[5];
+		uint32_t FLILL1; /* Flash Invalid Instructions Register, new since Sunrise Point/100 */
    	struct {
-			struct { /* FLREG0 Flash Descriptor */
-				uint32_t reg0_base	:13,
-							:3,
-					 reg0_limit	:13,
-							:3;
-			};
-			struct { /* FLREG1 BIOS */
-				uint32_t reg1_base	:13,
-							:3,
-					 reg1_limit	:13,
-							:3;
-			};
-			struct { /* FLREG2 ME */
-				uint32_t reg2_base	:13,
-							:3,
-					 reg2_limit	:13,
-							:3;
-			};
-			struct { /* FLREG3 GbE */
-				uint32_t reg3_base	:13,
-							:3,
-					 reg3_limit	:13,
-							:3;
-			};
-			struct { /* FLREG4 Platform */
-				uint32_t reg4_base	:13,
-							:3,
-					 reg4_limit	:13,
-							:3;
-			};
+			uint32_t invalid_instr4	:8,
+				 invalid_instr5	:8,
+				 invalid_instr6	:8,
+				 invalid_instr7	:8;
    	};
    };
 };

-struct ich_desc_master {
-	union {
-		uint32_t FLMSTR1;
-		struct {
-			uint32_t BIOS_req_ID	:16,
-				 BIOS_descr_r	:1,
-				 BIOS_BIOS_r	:1,
-				 BIOS_ME_r	:1,
-				 BIOS_GbE_r	:1,
-				 BIOS_plat_r	:1,
-						:3,
-				 BIOS_descr_w	:1,
-				 BIOS_BIOS_w	:1,
-				 BIOS_ME_w	:1,
-				 BIOS_GbE_w	:1,
-				 BIOS_plat_w	:1,
-						:3;
+#define MAX_NUM_FLREGS 10 /* 16 on unsupported Lewisburg PCH */
+union ich_desc_region {
+	uint32_t FLREG[MAX_NUM_FLREGS]; /* Flash Descriptor Regions */
+	/*
+	 * Number of entries and width differ on various generations:
+	 *
+	 * Chipset/Generation				#FLREGs		width (bits)
+	 * ICH8			.. Panther Point/7	 5		13
+	 * Lynx Point/8		.. Wildcat Point/9	 7		15
+	 * Sunrise Point/100	..			10		15
+	 */
+	struct {
+		uint32_t base	:15,
+				:1,
+			 limit	:15,
+				:1;
+	} reg[MAX_NUM_FLREGS];
+};
+
+union ich_desc_master {
+	/* For pre-Skylake platforms */
+	struct {
+		union {
+			uint32_t FLMSTR1;
+			struct {
+				uint32_t BIOS_req_ID	:16,
+					 BIOS_descr_r	:1,
+					 BIOS_BIOS_r	:1,
+					 BIOS_ME_r	:1,
+					 BIOS_GbE_r	:1,
+					 BIOS_plat_r	:1,
+							:3,
+					 BIOS_descr_w	:1,
+					 BIOS_BIOS_w	:1,
+					 BIOS_ME_w	:1,
+					 BIOS_GbE_w	:1,
+					 BIOS_plat_w	:1,
+							:3;
+			};
+		};
+		union {
+			uint32_t FLMSTR2;
+			struct {
+				uint32_t ME_req_ID	:16,
+					 ME_descr_r	:1,
+					 ME_BIOS_r	:1,
+					 ME_ME_r	:1,
+					 ME_GbE_r	:1,
+					 ME_plat_r	:1,
+							:3,
+					 ME_descr_w	:1,
+					 ME_BIOS_w	:1,
+					 ME_ME_w	:1,
+					 ME_GbE_w	:1,
+					 ME_plat_w	:1,
+							:3;
+			};
+		};
+		union {
+			uint32_t FLMSTR3;
+			struct {
+				uint32_t GbE_req_ID	:16,
+					 GbE_descr_r	:1,
+					 GbE_BIOS_r	:1,
+					 GbE_ME_r	:1,
+					 GbE_GbE_r	:1,
+					 GbE_plat_r	:1,
+							:3,
+					 GbE_descr_w	:1,
+					 GbE_BIOS_w	:1,
+					 GbE_ME_w	:1,
+					 GbE_GbE_w	:1,
+					 GbE_plat_w	:1,
+							:3;
+			};
    	};
    };
+	/* From Skylake on */
+	#define MAX_NUM_MASTERS 5 /* 6 on unsupported Lewisburg PCH */
    union {
-		uint32_t FLMSTR2;
+		uint32_t FLMSTR[MAX_NUM_MASTERS]; /* Flash Masters */
    	struct {
-			uint32_t ME_req_ID	:16,
-				 ME_descr_r	:1,
-				 ME_BIOS_r	:1,
-				 ME_ME_r	:1,
-				 ME_GbE_r	:1,
-				 ME_plat_r	:1,
-						:3,
-				 ME_descr_w	:1,
-				 ME_BIOS_w	:1,
-				 ME_ME_w	:1,
-				 ME_GbE_w	:1,
-				 ME_plat_w	:1,
-						:3;
-		};
-	};
-	union {
-		uint32_t FLMSTR3;
-		struct {
-			uint32_t GbE_req_ID	:16,
-				 GbE_descr_r	:1,
-				 GbE_BIOS_r	:1,
-				 GbE_ME_r	:1,
-				 GbE_GbE_r	:1,
-				 GbE_plat_r	:1,
-						:3,
-				 GbE_descr_w	:1,
-				 GbE_BIOS_w	:1,
-				 GbE_ME_w	:1,
-				 GbE_GbE_w	:1,
-				 GbE_plat_w	:1,
-						:3;
-		};
+			uint32_t	:8,
+				 read	:12,
+				 write	:12;
+		} master[MAX_NUM_MASTERS];
    };
 };