Change in flashrom[staging]: Handle Intel Wildcat Point *LP* like Lynx Point LP

[Nico Huber (Code Review)]

Nico Huber has submitted this change and it was merged. ( https://review.coreboot.org/18883 )

Change subject: Handle Intel Wildcat Point *LP* like Lynx Point LP
......................................................................

Handle Intel Wildcat Point *LP* like Lynx Point LP

The subtle difference was ignored when adding these chipsets. The
integrated Wildcat Point LP PCH is documented in [1].

I'm not sure how to account for "Broadwell H" which seems not publicly
documented. Maybe it's an unreleased HM9*, in which case the non-LP
path should be correct.

[1] Mobile 5th Generation Intel® Core(TM) Processor Family I/O,
    Intel® Core(TM) M Processor Family I/O, Mobile Intel® Pentium® Processor
    Family I/O, and Mobile Intel® Celeron® Processor Family I/O Datasheet
    Revision 004
    Document Number: 330837

Change-Id: I6b7ca3c0bde111b04ed7c745ed76d28d3d05f01c
Signed-off-by: Nico Huber 
Reviewed-on: https://review.coreboot.org/18883
Reviewed-by: Youness Alaoui 
Reviewed-by: David Hendricks 
Reviewed-by: Philippe Mathieu-Daudé 
Tested-by: build bot (Jenkins) 
---
M chipset_enable.c
M ich_descriptors.c
M programmer.h
3 files changed, 21 insertions(+), 9 deletions(-)

Approvals:
  Youness Alaoui: Looks good to me, but someone else must approve
  David Hendricks: Looks good to me, approved
  Philippe Mathieu-Daudé: Looks good to me, but someone else must approve
  build bot (Jenkins): Verified

diff --git a/chipset_enable.c b/chipset_enable.c
index 1191a4c..208cd3a 100644
--- a/chipset_enable.c
+++ b/chipset_enable.c
@@ -643,6 +643,7 @@
    	straps_names = straps_names_pch89_baytrail;
    	break;
    case CHIPSET_8_SERIES_LYNX_POINT_LP:
+	case CHIPSET_9_SERIES_WILDCAT_POINT_LP:
    	straps_names = straps_names_pch8_lp;
    	break;
    case CHIPSET_8_SERIES_WELLSBURG: // FIXME: check datasheet
@@ -661,7 +662,8 @@
    	bbs = (gcs >> 1) & 0x1;
    	break;
    case CHIPSET_8_SERIES_LYNX_POINT_LP:
-		/* Lynx Point LP uses a single bit for BBS */
+	case CHIPSET_9_SERIES_WILDCAT_POINT_LP:
+		/* LP PCHs use a single bit for BBS */
    	bbs = (gcs >> 10) & 0x1;
    	break;
    default:
@@ -796,6 +798,12 @@
 static int enable_flash_pch9(struct pci_dev *dev, const char *name)
 {
    return enable_flash_ich_spi(dev, CHIPSET_9_SERIES_WILDCAT_POINT, 0xdc);
+}
+
+/* Wildcat Point LP */
+static int enable_flash_pch9_lp(struct pci_dev *dev, const char *name)
+{
+	return enable_flash_ich_spi(dev, CHIPSET_9_SERIES_WILDCAT_POINT_LP, 0xdc);
 }

/* Silvermont architecture: Bay Trail(-T/-I), Avoton/Rangeley.
@@ -1787,13 +1795,13 @@
    {0x8086, 0x9c43, NT,  "Intel", "Lynx Point LP Premium",		enable_flash_pch8_lp},
    {0x8086, 0x9c45, NT,  "Intel", "Lynx Point LP Mainstream",	enable_flash_pch8_lp},
    {0x8086, 0x9c47, NT,  "Intel", "Lynx Point LP Value",		enable_flash_pch8_lp},
-	{0x8086, 0x9cc1, NT,  "Intel", "Haswell U Sample",		enable_flash_pch9},
-	{0x8086, 0x9cc2, NT,  "Intel", "Broadwell U Sample",		enable_flash_pch9},
-	{0x8086, 0x9cc3, NT,  "Intel", "Broadwell U Premium",		enable_flash_pch9},
-	{0x8086, 0x9cc5, NT,  "Intel", "Broadwell U Base",		enable_flash_pch9},
-	{0x8086, 0x9cc6, NT,  "Intel", "Broadwell Y Sample",		enable_flash_pch9},
-	{0x8086, 0x9cc7, NT,  "Intel", "Broadwell Y Premium",		enable_flash_pch9},
-	{0x8086, 0x9cc9, NT,  "Intel", "Broadwell Y Base",		enable_flash_pch9},
+	{0x8086, 0x9cc1, NT,  "Intel", "Haswell U Sample",		enable_flash_pch9_lp},
+	{0x8086, 0x9cc2, NT,  "Intel", "Broadwell U Sample",		enable_flash_pch9_lp},
+	{0x8086, 0x9cc3, NT,  "Intel", "Broadwell U Premium",		enable_flash_pch9_lp},
+	{0x8086, 0x9cc5, NT,  "Intel", "Broadwell U Base",		enable_flash_pch9_lp},
+	{0x8086, 0x9cc6, NT,  "Intel", "Broadwell Y Sample",		enable_flash_pch9_lp},
+	{0x8086, 0x9cc7, NT,  "Intel", "Broadwell Y Premium",		enable_flash_pch9_lp},
+	{0x8086, 0x9cc9, NT,  "Intel", "Broadwell Y Base",		enable_flash_pch9_lp},
    {0x8086, 0x9ccb, NT,  "Intel", "Broadwell H",			enable_flash_pch9},
    {0x8086, 0x9d41, BAD, "Intel", "Sunrise Point (Skylake LP Sample)",	NULL},
    {0x8086, 0x9d43, BAD, "Intel", "Sunrise Point (Skylake-U Base)",	NULL},
diff --git a/ich_descriptors.c b/ich_descriptors.c
index 7e2521a..34100cb 100644
--- a/ich_descriptors.c
+++ b/ich_descriptors.c
@@ -139,7 +139,8 @@
    case CHIPSET_8_SERIES_LYNX_POINT:
    case CHIPSET_8_SERIES_LYNX_POINT_LP:
    case CHIPSET_8_SERIES_WELLSBURG:
-	case CHIPSET_9_SERIES_WILDCAT_POINT: {
+	case CHIPSET_9_SERIES_WILDCAT_POINT:
+	case CHIPSET_9_SERIES_WILDCAT_POINT_LP: {
    	uint8_t size_enc;
    	if (idx == 0) {
    		size_enc = desc->component.dens_new.comp1_density;
@@ -183,6 +184,7 @@
    case CHIPSET_8_SERIES_LYNX_POINT_LP:
    case CHIPSET_8_SERIES_WELLSBURG:
    case CHIPSET_9_SERIES_WILDCAT_POINT:
+	case CHIPSET_9_SERIES_WILDCAT_POINT_LP:
    	return freq_str[value];
    case CHIPSET_ICH_UNKNOWN:
    default:
@@ -821,6 +823,7 @@
    case CHIPSET_8_SERIES_LYNX_POINT_LP:
    case CHIPSET_8_SERIES_WELLSBURG:
    case CHIPSET_9_SERIES_WILDCAT_POINT:
+	case CHIPSET_9_SERIES_WILDCAT_POINT_LP:
    	if (idx == 0) {
    		size_enc = desc->component.dens_new.comp1_density;
    	} else {
diff --git a/programmer.h b/programmer.h
index 1a6216a..9beaf98 100644
--- a/programmer.h
+++ b/programmer.h
@@ -649,6 +649,7 @@
    CHIPSET_8_SERIES_LYNX_POINT_LP,
    CHIPSET_8_SERIES_WELLSBURG,
    CHIPSET_9_SERIES_WILDCAT_POINT,
+	CHIPSET_9_SERIES_WILDCAT_POINT_LP,
 };

/* ichspi.c */