Nico Huber has submitted this change. ( https://review.coreboot.org/c/flashrom/+/61160 )
Change subject: hwaccess: move mmio functions into hwaccess_physmap ......................................................................
hwaccess: move mmio functions into hwaccess_physmap
The mmio_le/be_read/writex functions are used for raw memory access. Bundle them with the physmap functions.
Change-Id: I313062b078e89630c703038866ac93c651f0f49a Signed-off-by: Thomas Heijligen thomas.heijligen@secunet.com Reviewed-on: https://review.coreboot.org/c/flashrom/+/61160 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Nico Huber nico.h@gmx.de --- M Makefile M atapromise.c M board_enable.c M chipset_enable.c M dmi.c M drkaiser.c M flashrom.c M gfxnvidia.c D hwaccess.c M hwaccess.h M hwaccess_physmap.c M hwaccess_physmap.h M ich_descriptors.c M ichspi.c M internal.c M it8212.c M it87spi.c M libflashrom.c M mcp6x_spi.c M meson.build M nicintel.c M nicintel_eeprom.c M nicintel_spi.c M ogp_spi.c M satamv.c M satasii.c M sb600spi.c M wbsio_spi.c 28 files changed, 249 insertions(+), 293 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved
diff --git a/Makefile b/Makefile index b8287a9..6e2e33f 100644 --- a/Makefile +++ b/Makefile @@ -833,7 +833,7 @@ ifneq ($(NEED_RAW_ACCESS), ) # Raw memory, MSR or PCI port I/O access. FEATURE_CFLAGS += -D'NEED_RAW_ACCESS=1' -PROGRAMMER_OBJS += hwaccess.o hwaccess_physmap.o +PROGRAMMER_OBJS += hwaccess_physmap.o
ifeq ($(ARCH), x86) FEATURE_CFLAGS += -D'__FLASHROM_HAVE_OUTB__=1' diff --git a/atapromise.c b/atapromise.c index fb3adcb..d781190 100644 --- a/atapromise.c +++ b/atapromise.c @@ -18,7 +18,6 @@ #include <stdlib.h> #include "flash.h" #include "programmer.h" -#include "hwaccess.h" #include "hwaccess_x86_io.h" #include "hwaccess_physmap.h" #include "platform/pci.h" diff --git a/board_enable.c b/board_enable.c index 445e354..c23e257 100644 --- a/board_enable.c +++ b/board_enable.c @@ -25,7 +25,6 @@ #include <stdlib.h> #include "flash.h" #include "programmer.h" -#include "hwaccess.h" #include "hwaccess_x86_io.h" #include "hwaccess_x86_msr.h" #include "platform/pci.h" diff --git a/chipset_enable.c b/chipset_enable.c index 02a93a8..d72300e 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -33,7 +33,6 @@ #include <errno.h> #include "flash.h" #include "programmer.h" -#include "hwaccess.h" #include "hwaccess_x86_io.h" #include "hwaccess_x86_msr.h" #include "hwaccess_physmap.h" diff --git a/dmi.c b/dmi.c index df918f9..16d350d 100644 --- a/dmi.c +++ b/dmi.c @@ -31,7 +31,6 @@ #include <stdlib.h>
#include "flash.h" -#include "hwaccess.h" #include "hwaccess_physmap.h" #include "programmer.h"
diff --git a/drkaiser.c b/drkaiser.c index 3738930..0849109 100644 --- a/drkaiser.c +++ b/drkaiser.c @@ -17,7 +17,6 @@ #include <stdlib.h> #include "flash.h" #include "programmer.h" -#include "hwaccess.h" #include "hwaccess_physmap.h" #include "platform/pci.h"
diff --git a/flashrom.c b/flashrom.c index 73ebab5..bd34676 100644 --- a/flashrom.c +++ b/flashrom.c @@ -37,7 +37,6 @@ #include "flash.h" #include "flashchips.h" #include "programmer.h" -#include "hwaccess.h" #include "hwaccess_physmap.h" #include "chipdrivers.h"
diff --git a/gfxnvidia.c b/gfxnvidia.c index 535467e..e5c07dd 100644 --- a/gfxnvidia.c +++ b/gfxnvidia.c @@ -18,7 +18,6 @@ #include <string.h> #include "flash.h" #include "programmer.h" -#include "hwaccess.h" #include "hwaccess_physmap.h" #include "platform/pci.h"
diff --git a/hwaccess.c b/hwaccess.c deleted file mode 100644 index 4e8a274..0000000 --- a/hwaccess.c +++ /dev/null @@ -1,237 +0,0 @@ -/* - * This file is part of the flashrom project. - * - * Copyright (C) 2009,2010 Carl-Daniel Hailfinger - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <string.h> -#include <stdlib.h> -#include <errno.h> -#include <sys/types.h> -#if !defined (__DJGPP__) && !defined(__LIBPAYLOAD__) -/* No file access needed/possible to get hardware access permissions. */ -#include <unistd.h> -#include <fcntl.h> -#endif -#include "flash.h" -#include "hwaccess.h" - -/* Prevent reordering and/or merging of reads/writes to hardware. - * Such reordering and/or merging would break device accesses which depend on the exact access order. - */ -static inline void sync_primitive(void) -{ -/* This is not needed for... - * - x86: uses uncached accesses which have a strongly ordered memory model. - * - MIPS: uses uncached accesses in mode 2 on /dev/mem which has also a strongly ordered memory model. - * - ARM: uses a strongly ordered memory model for device memories. - * - * See also https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/Documen... - */ -// cf. http://lxr.free-electrons.com/source/arch/powerpc/include/asm/barrier.h -#if defined(__powerpc) || defined(__powerpc__) || defined(__powerpc64__) || defined(__POWERPC__) || \ - defined(__ppc__) || defined(__ppc64__) || defined(_M_PPC) || defined(_ARCH_PPC) || \ - defined(_ARCH_PPC64) || defined(__ppc) - asm("eieio" : : : "memory"); -#elif (__sparc__) || defined (__sparc) -#if defined(__sparc_v9__) || defined(__sparcv9) - /* Sparc V9 CPUs support three different memory orderings that range from x86-like TSO to PowerPC-like - * RMO. The modes can be switched at runtime thus to make sure we maintain the right order of access we - * use the strongest hardware memory barriers that exist on Sparc V9. */ - asm volatile ("membar #Sync" ::: "memory"); -#elif defined(__sparc_v8__) || defined(__sparcv8) - /* On SPARC V8 there is no RMO just PSO and that does not apply to I/O accesses... but if V8 code is run - * on V9 CPUs it might apply... or not... we issue a write barrier anyway. That's the most suitable - * operation in the V8 instruction set anyway. If you know better then please tell us. */ - asm volatile ("stbar"); -#else - #error Unknown and/or unsupported SPARC instruction set version detected. -#endif -#endif -} - -void mmio_writeb(uint8_t val, void *addr) -{ - *(volatile uint8_t *) addr = val; - sync_primitive(); -} - -void mmio_writew(uint16_t val, void *addr) -{ - *(volatile uint16_t *) addr = val; - sync_primitive(); -} - -void mmio_writel(uint32_t val, void *addr) -{ - *(volatile uint32_t *) addr = val; - sync_primitive(); -} - -uint8_t mmio_readb(const void *addr) -{ - return *(volatile const uint8_t *) addr; -} - -uint16_t mmio_readw(const void *addr) -{ - return *(volatile const uint16_t *) addr; -} - -uint32_t mmio_readl(const void *addr) -{ - return *(volatile const uint32_t *) addr; -} - -void mmio_readn(const void *addr, uint8_t *buf, size_t len) -{ - memcpy(buf, addr, len); - return; -} - -void mmio_le_writeb(uint8_t val, void *addr) -{ - mmio_writeb(cpu_to_le8(val), addr); -} - -void mmio_le_writew(uint16_t val, void *addr) -{ - mmio_writew(cpu_to_le16(val), addr); -} - -void mmio_le_writel(uint32_t val, void *addr) -{ - mmio_writel(cpu_to_le32(val), addr); -} - -uint8_t mmio_le_readb(const void *addr) -{ - return le_to_cpu8(mmio_readb(addr)); -} - -uint16_t mmio_le_readw(const void *addr) -{ - return le_to_cpu16(mmio_readw(addr)); -} - -uint32_t mmio_le_readl(const void *addr) -{ - return le_to_cpu32(mmio_readl(addr)); -} - -enum mmio_write_type { - mmio_write_type_b, - mmio_write_type_w, - mmio_write_type_l, -}; - -struct undo_mmio_write_data { - void *addr; - int reg; - enum mmio_write_type type; - union { - uint8_t bdata; - uint16_t wdata; - uint32_t ldata; - }; -}; - -static int undo_mmio_write(void *p) -{ - struct undo_mmio_write_data *data = p; - msg_pdbg("Restoring MMIO space at %p\n", data->addr); - switch (data->type) { - case mmio_write_type_b: - mmio_writeb(data->bdata, data->addr); - break; - case mmio_write_type_w: - mmio_writew(data->wdata, data->addr); - break; - case mmio_write_type_l: - mmio_writel(data->ldata, data->addr); - break; - } - /* p was allocated in register_undo_mmio_write. */ - free(p); - return 0; -} - -#define register_undo_mmio_write(a, c) \ -{ \ - struct undo_mmio_write_data *undo_mmio_write_data; \ - undo_mmio_write_data = malloc(sizeof(*undo_mmio_write_data)); \ - if (!undo_mmio_write_data) { \ - msg_gerr("Out of memory!\n"); \ - exit(1); \ - } \ - undo_mmio_write_data->addr = a; \ - undo_mmio_write_data->type = mmio_write_type_##c; \ - undo_mmio_write_data->c##data = mmio_read##c(a); \ - register_shutdown(undo_mmio_write, undo_mmio_write_data); \ -} - -#define register_undo_mmio_writeb(a) register_undo_mmio_write(a, b) -#define register_undo_mmio_writew(a) register_undo_mmio_write(a, w) -#define register_undo_mmio_writel(a) register_undo_mmio_write(a, l) - -void rmmio_writeb(uint8_t val, void *addr) -{ - register_undo_mmio_writeb(addr); - mmio_writeb(val, addr); -} - -void rmmio_writew(uint16_t val, void *addr) -{ - register_undo_mmio_writew(addr); - mmio_writew(val, addr); -} - -void rmmio_writel(uint32_t val, void *addr) -{ - register_undo_mmio_writel(addr); - mmio_writel(val, addr); -} - -void rmmio_le_writeb(uint8_t val, void *addr) -{ - register_undo_mmio_writeb(addr); - mmio_le_writeb(val, addr); -} - -void rmmio_le_writew(uint16_t val, void *addr) -{ - register_undo_mmio_writew(addr); - mmio_le_writew(val, addr); -} - -void rmmio_le_writel(uint32_t val, void *addr) -{ - register_undo_mmio_writel(addr); - mmio_le_writel(val, addr); -} - -void rmmio_valb(void *addr) -{ - register_undo_mmio_writeb(addr); -} - -void rmmio_valw(void *addr) -{ - register_undo_mmio_writew(addr); -} - -void rmmio_vall(void *addr) -{ - register_undo_mmio_writel(addr); -} diff --git a/hwaccess.h b/hwaccess.h index d80e0e3..98ca08e 100644 --- a/hwaccess.h +++ b/hwaccess.h @@ -20,38 +20,6 @@ #ifndef __HWACCESS_H__ #define __HWACCESS_H__ 1
-void mmio_writeb(uint8_t val, void *addr); -void mmio_writew(uint16_t val, void *addr); -void mmio_writel(uint32_t val, void *addr); -uint8_t mmio_readb(const void *addr); -uint16_t mmio_readw(const void *addr); -uint32_t mmio_readl(const void *addr); -void mmio_readn(const void *addr, uint8_t *buf, size_t len); -void mmio_le_writeb(uint8_t val, void *addr); -void mmio_le_writew(uint16_t val, void *addr); -void mmio_le_writel(uint32_t val, void *addr); -uint8_t mmio_le_readb(const void *addr); -uint16_t mmio_le_readw(const void *addr); -uint32_t mmio_le_readl(const void *addr); -#define pci_mmio_writeb mmio_le_writeb -#define pci_mmio_writew mmio_le_writew -#define pci_mmio_writel mmio_le_writel -#define pci_mmio_readb mmio_le_readb -#define pci_mmio_readw mmio_le_readw -#define pci_mmio_readl mmio_le_readl -void rmmio_writeb(uint8_t val, void *addr); -void rmmio_writew(uint16_t val, void *addr); -void rmmio_writel(uint32_t val, void *addr); -void rmmio_le_writeb(uint8_t val, void *addr); -void rmmio_le_writew(uint16_t val, void *addr); -void rmmio_le_writel(uint32_t val, void *addr); -#define pci_rmmio_writeb rmmio_le_writeb -#define pci_rmmio_writew rmmio_le_writew -#define pci_rmmio_writel rmmio_le_writel -void rmmio_valb(void *addr); -void rmmio_valw(void *addr); -void rmmio_vall(void *addr); - #define ___constant_swab8(x) ((uint8_t) ( \ (((uint8_t)(x) & (uint8_t)0xffU))))
diff --git a/hwaccess_physmap.c b/hwaccess_physmap.c index dcc6ed7..b1b9c64 100644 --- a/hwaccess_physmap.c +++ b/hwaccess_physmap.c @@ -18,16 +18,20 @@
#include <unistd.h> #include <stdbool.h> +#include <stdint.h> #include <stdio.h> #include <stdlib.h> #include <string.h> #include <errno.h> #include "flash.h" +#include "hwaccess.h" #include "hwaccess_physmap.h"
#if !defined(__DJGPP__) && !defined(__LIBPAYLOAD__) /* No file access needed/possible to get mmap access permissions or access MSR. */ +#include <unistd.h> #include <sys/stat.h> +#include <sys/types.h> #include <fcntl.h> #endif
@@ -361,3 +365,212 @@ { return physmap_common(descr, phys_addr, len, PHYSM_RO, PHYSM_NOCLEANUP, PHYSM_EXACT); } + +/* Prevent reordering and/or merging of reads/writes to hardware. + * Such reordering and/or merging would break device accesses which depend on the exact access order. + */ +static inline void sync_primitive(void) +{ +/* This is not needed for... + * - x86: uses uncached accesses which have a strongly ordered memory model. + * - MIPS: uses uncached accesses in mode 2 on /dev/mem which has also a strongly ordered memory model. + * - ARM: uses a strongly ordered memory model for device memories. + * + * See also https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/Documen... + */ +// cf. http://lxr.free-electrons.com/source/arch/powerpc/include/asm/barrier.h +#if defined(__powerpc) || defined(__powerpc__) || defined(__powerpc64__) || defined(__POWERPC__) || \ + defined(__ppc__) || defined(__ppc64__) || defined(_M_PPC) || defined(_ARCH_PPC) || \ + defined(_ARCH_PPC64) || defined(__ppc) + asm("eieio" : : : "memory"); +#elif (__sparc__) || defined (__sparc) +#if defined(__sparc_v9__) || defined(__sparcv9) + /* Sparc V9 CPUs support three different memory orderings that range from x86-like TSO to PowerPC-like + * RMO. The modes can be switched at runtime thus to make sure we maintain the right order of access we + * use the strongest hardware memory barriers that exist on Sparc V9. */ + asm volatile ("membar #Sync" ::: "memory"); +#elif defined(__sparc_v8__) || defined(__sparcv8) + /* On SPARC V8 there is no RMO just PSO and that does not apply to I/O accesses... but if V8 code is run + * on V9 CPUs it might apply... or not... we issue a write barrier anyway. That's the most suitable + * operation in the V8 instruction set anyway. If you know better then please tell us. */ + asm volatile ("stbar"); +#else + #error Unknown and/or unsupported SPARC instruction set version detected. +#endif +#endif +} + +void mmio_writeb(uint8_t val, void *addr) +{ + *(volatile uint8_t *) addr = val; + sync_primitive(); +} + +void mmio_writew(uint16_t val, void *addr) +{ + *(volatile uint16_t *) addr = val; + sync_primitive(); +} + +void mmio_writel(uint32_t val, void *addr) +{ + *(volatile uint32_t *) addr = val; + sync_primitive(); +} + +uint8_t mmio_readb(const void *addr) +{ + return *(volatile const uint8_t *) addr; +} + +uint16_t mmio_readw(const void *addr) +{ + return *(volatile const uint16_t *) addr; +} + +uint32_t mmio_readl(const void *addr) +{ + return *(volatile const uint32_t *) addr; +} + +void mmio_readn(const void *addr, uint8_t *buf, size_t len) +{ + memcpy(buf, addr, len); + return; +} + +void mmio_le_writeb(uint8_t val, void *addr) +{ + mmio_writeb(cpu_to_le8(val), addr); +} + +void mmio_le_writew(uint16_t val, void *addr) +{ + mmio_writew(cpu_to_le16(val), addr); +} + +void mmio_le_writel(uint32_t val, void *addr) +{ + mmio_writel(cpu_to_le32(val), addr); +} + +uint8_t mmio_le_readb(const void *addr) +{ + return le_to_cpu8(mmio_readb(addr)); +} + +uint16_t mmio_le_readw(const void *addr) +{ + return le_to_cpu16(mmio_readw(addr)); +} + +uint32_t mmio_le_readl(const void *addr) +{ + return le_to_cpu32(mmio_readl(addr)); +} + +enum mmio_write_type { + mmio_write_type_b, + mmio_write_type_w, + mmio_write_type_l, +}; + +struct undo_mmio_write_data { + void *addr; + int reg; + enum mmio_write_type type; + union { + uint8_t bdata; + uint16_t wdata; + uint32_t ldata; + }; +}; + +static int undo_mmio_write(void *p) +{ + struct undo_mmio_write_data *data = p; + msg_pdbg("Restoring MMIO space at %p\n", data->addr); + switch (data->type) { + case mmio_write_type_b: + mmio_writeb(data->bdata, data->addr); + break; + case mmio_write_type_w: + mmio_writew(data->wdata, data->addr); + break; + case mmio_write_type_l: + mmio_writel(data->ldata, data->addr); + break; + } + /* p was allocated in register_undo_mmio_write. */ + free(p); + return 0; +} + +#define register_undo_mmio_write(a, c) \ +{ \ + struct undo_mmio_write_data *undo_mmio_write_data; \ + undo_mmio_write_data = malloc(sizeof(*undo_mmio_write_data)); \ + if (!undo_mmio_write_data) { \ + msg_gerr("Out of memory!\n"); \ + exit(1); \ + } \ + undo_mmio_write_data->addr = a; \ + undo_mmio_write_data->type = mmio_write_type_##c; \ + undo_mmio_write_data->c##data = mmio_read##c(a); \ + register_shutdown(undo_mmio_write, undo_mmio_write_data); \ +} + +#define register_undo_mmio_writeb(a) register_undo_mmio_write(a, b) +#define register_undo_mmio_writew(a) register_undo_mmio_write(a, w) +#define register_undo_mmio_writel(a) register_undo_mmio_write(a, l) + +void rmmio_writeb(uint8_t val, void *addr) +{ + register_undo_mmio_writeb(addr); + mmio_writeb(val, addr); +} + +void rmmio_writew(uint16_t val, void *addr) +{ + register_undo_mmio_writew(addr); + mmio_writew(val, addr); +} + +void rmmio_writel(uint32_t val, void *addr) +{ + register_undo_mmio_writel(addr); + mmio_writel(val, addr); +} + +void rmmio_le_writeb(uint8_t val, void *addr) +{ + register_undo_mmio_writeb(addr); + mmio_le_writeb(val, addr); +} + +void rmmio_le_writew(uint16_t val, void *addr) +{ + register_undo_mmio_writew(addr); + mmio_le_writew(val, addr); +} + +void rmmio_le_writel(uint32_t val, void *addr) +{ + register_undo_mmio_writel(addr); + mmio_le_writel(val, addr); +} + +void rmmio_valb(void *addr) +{ + register_undo_mmio_writeb(addr); +} + +void rmmio_valw(void *addr) +{ + register_undo_mmio_writew(addr); +} + +void rmmio_vall(void *addr) +{ + register_undo_mmio_writel(addr); +} diff --git a/hwaccess_physmap.h b/hwaccess_physmap.h index eb3ddb8..a0a7e74 100644 --- a/hwaccess_physmap.h +++ b/hwaccess_physmap.h @@ -24,4 +24,36 @@ void physunmap(void *virt_addr, size_t len); void physunmap_unaligned(void *virt_addr, size_t len);
+void mmio_writeb(uint8_t val, void *addr); +void mmio_writew(uint16_t val, void *addr); +void mmio_writel(uint32_t val, void *addr); +uint8_t mmio_readb(const void *addr); +uint16_t mmio_readw(const void *addr); +uint32_t mmio_readl(const void *addr); +void mmio_readn(const void *addr, uint8_t *buf, size_t len); +void mmio_le_writeb(uint8_t val, void *addr); +void mmio_le_writew(uint16_t val, void *addr); +void mmio_le_writel(uint32_t val, void *addr); +uint8_t mmio_le_readb(const void *addr); +uint16_t mmio_le_readw(const void *addr); +uint32_t mmio_le_readl(const void *addr); +#define pci_mmio_writeb mmio_le_writeb +#define pci_mmio_writew mmio_le_writew +#define pci_mmio_writel mmio_le_writel +#define pci_mmio_readb mmio_le_readb +#define pci_mmio_readw mmio_le_readw +#define pci_mmio_readl mmio_le_readl +void rmmio_writeb(uint8_t val, void *addr); +void rmmio_writew(uint16_t val, void *addr); +void rmmio_writel(uint32_t val, void *addr); +void rmmio_le_writeb(uint8_t val, void *addr); +void rmmio_le_writew(uint16_t val, void *addr); +void rmmio_le_writel(uint32_t val, void *addr); +#define pci_rmmio_writeb rmmio_le_writeb +#define pci_rmmio_writew rmmio_le_writew +#define pci_rmmio_writel rmmio_le_writel +void rmmio_valb(void *addr); +void rmmio_valw(void *addr); +void rmmio_vall(void *addr); + #endif /* __HWACCESS_PHYSMAP_H__ */ \ No newline at end of file diff --git a/ich_descriptors.c b/ich_descriptors.c index 56a3c67..2bff341 100644 --- a/ich_descriptors.c +++ b/ich_descriptors.c @@ -15,8 +15,8 @@ * GNU General Public License for more details. */
+#include "hwaccess_physmap.h" #include "ich_descriptors.h" -#include "hwaccess.h"
#ifdef ICH_DESCRIPTORS_FROM_DUMP_ONLY #include <stdio.h> diff --git a/ichspi.c b/ichspi.c index 0bb6360..47b23eb 100644 --- a/ichspi.c +++ b/ichspi.c @@ -23,7 +23,6 @@ #include <stdlib.h> #include "flash.h" #include "programmer.h" -#include "hwaccess.h" #include "hwaccess_physmap.h" #include "spi.h" #include "ich_descriptors.h" diff --git a/internal.c b/internal.c index f2f1fb1..bb606ca 100644 --- a/internal.c +++ b/internal.c @@ -19,7 +19,6 @@ #include <stdlib.h> #include "flash.h" #include "programmer.h" -#include "hwaccess.h" #include "hwaccess_x86_io.h" #include "hwaccess_physmap.h" #include "platform/pci.h" diff --git a/it8212.c b/it8212.c index ca82d9c..e57397a 100644 --- a/it8212.c +++ b/it8212.c @@ -17,7 +17,6 @@ #include <stdlib.h> #include "flash.h" #include "programmer.h" -#include "hwaccess.h" #include "hwaccess_physmap.h" #include "platform/pci.h"
diff --git a/it87spi.c b/it87spi.c index 0944915..728ec70 100644 --- a/it87spi.c +++ b/it87spi.c @@ -25,7 +25,7 @@ #include "flash.h" #include "chipdrivers.h" #include "programmer.h" -#include "hwaccess.h" +#include "hwaccess_physmap.h" #include "hwaccess_x86_io.h" #include "spi.h"
diff --git a/libflashrom.c b/libflashrom.c index 1ecf650..fb70934 100644 --- a/libflashrom.c +++ b/libflashrom.c @@ -29,7 +29,6 @@ #include "fmap.h" #include "programmer.h" #include "layout.h" -#include "hwaccess.h" #include "ich_descriptors.h" #include "libflashrom.h"
diff --git a/mcp6x_spi.c b/mcp6x_spi.c index 2097cf4..81ef1b5 100644 --- a/mcp6x_spi.c +++ b/mcp6x_spi.c @@ -23,7 +23,6 @@ #include <ctype.h> #include "flash.h" #include "programmer.h" -#include "hwaccess.h" #include "hwaccess_physmap.h" #include "platform/pci.h"
diff --git a/meson.build b/meson.build index b2e2d72..403a33e 100644 --- a/meson.build +++ b/meson.build @@ -346,7 +346,6 @@
# raw memory, MSR or PCI port I/O access if need_raw_access - srcs += 'hwaccess.c' srcs += 'hwaccess_x86_io.c' srcs += 'hwaccess_x86_msr.c' srcs += 'hwaccess_physmap.c' diff --git a/nicintel.c b/nicintel.c index c8a8789..fdc4eba 100644 --- a/nicintel.c +++ b/nicintel.c @@ -18,7 +18,6 @@ #include <stdlib.h> #include "flash.h" #include "programmer.h" -#include "hwaccess.h" #include "hwaccess_physmap.h" #include "platform/pci.h"
diff --git a/nicintel_eeprom.c b/nicintel_eeprom.c index ea0e768..af5fa21 100644 --- a/nicintel_eeprom.c +++ b/nicintel_eeprom.c @@ -34,7 +34,6 @@ #include "flash.h" #include "spi.h" #include "programmer.h" -#include "hwaccess.h" #include "hwaccess_physmap.h" #include "platform/pci.h"
diff --git a/nicintel_spi.c b/nicintel_spi.c index 004af66..1f1dcff 100644 --- a/nicintel_spi.c +++ b/nicintel_spi.c @@ -34,7 +34,6 @@ #include <unistd.h> #include "flash.h" #include "programmer.h" -#include "hwaccess.h" #include "hwaccess_physmap.h" #include "platform/pci.h"
diff --git a/ogp_spi.c b/ogp_spi.c index 830cfe7..bc0d739 100644 --- a/ogp_spi.c +++ b/ogp_spi.c @@ -18,7 +18,6 @@ #include <string.h> #include "flash.h" #include "programmer.h" -#include "hwaccess.h" #include "hwaccess_physmap.h" #include "platform/pci.h"
diff --git a/satamv.c b/satamv.c index e7c4305..445b2c8 100644 --- a/satamv.c +++ b/satamv.c @@ -19,7 +19,6 @@ #include <stdlib.h> #include "flash.h" #include "programmer.h" -#include "hwaccess.h" #include "hwaccess_x86_io.h" #include "hwaccess_physmap.h" #include "platform/pci.h" diff --git a/satasii.c b/satasii.c index a27fc29..3ee5556 100644 --- a/satasii.c +++ b/satasii.c @@ -17,7 +17,6 @@ /* Datasheets can be found on http://www.siliconimage.com. Great thanks! */
#include "programmer.h" -#include "hwaccess.h" #include "hwaccess_physmap.h" #include "platform/pci.h"
diff --git a/sb600spi.c b/sb600spi.c index 32a7420..eb54028 100644 --- a/sb600spi.c +++ b/sb600spi.c @@ -22,7 +22,6 @@ #include <stdlib.h> #include "flash.h" #include "programmer.h" -#include "hwaccess.h" #include "hwaccess_physmap.h" #include "spi.h" #include "platform/pci.h" diff --git a/wbsio_spi.c b/wbsio_spi.c index 805abf7..2794491 100644 --- a/wbsio_spi.c +++ b/wbsio_spi.c @@ -19,7 +19,7 @@ #include "flash.h" #include "chipdrivers.h" #include "programmer.h" -#include "hwaccess.h" +#include "hwaccess_physmap.h" #include "hwaccess_x86_io.h" #include "spi.h"
-
Nico Huber (Code Review)