Change in flashrom[master]: Enable 4BA mode for Spansion 25FL256S

[Nico Huber (Code Review)]

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/25133

Change subject: Enable 4BA mode for Spansion 25FL256S
......................................................................

Enable 4BA mode for Spansion 25FL256S

4BA mode is entered by setting bit 7 for the extended address register.

Change-Id: I807bf55d65763a9f48a6a3377f14f4e5288a7a4c
Signed-off-by: Nico Huber 
---
M flash.h
M flashchips.c
M flashrom.c
M spi25.c
4 files changed, 10 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/flashrom refs/changes/33/25133/1

diff --git a/flash.h b/flash.h
index f8b420f..e0ce669 100644
--- a/flash.h
+++ b/flash.h
@@ -121,15 +121,17 @@
 #define FEATURE_QPI		(1 << 9)
 #define FEATURE_4BA_ENTER	(1 << 10) /**< Can enter/exit 4BA mode with instructions 0xb7/0xe9 w/o WREN */
 #define FEATURE_4BA_ENTER_WREN	(1 << 11) /**< Can enter/exit 4BA mode with instructions 0xb7/0xe9 after WREN */
-#define FEATURE_4BA_EXT_ADDR	(1 << 12) /**< Regular 3-byte operations can be used by writing the most
+#define FEATURE_4BA_ENTER_EAR7	(1 << 12) /**< Can enter/exit 4BA mode by setting bit7 of the ext addr reg */
+#define FEATURE_4BA_EXT_ADDR	(1 << 13) /**< Regular 3-byte operations can be used by writing the most
    				       significant address byte into an extended address register. */
-#define FEATURE_4BA_READ	(1 << 13) /**< Native 4BA read instruction (0x13) is supported. */
-#define FEATURE_4BA_FAST_READ	(1 << 14) /**< Native 4BA fast read instruction (0x0c) is supported. */
-#define FEATURE_4BA_WRITE	(1 << 15) /**< Native 4BA byte program (0x12) is supported. */
+#define FEATURE_4BA_READ	(1 << 14) /**< Native 4BA read instruction (0x13) is supported. */
+#define FEATURE_4BA_FAST_READ	(1 << 15) /**< Native 4BA fast read instruction (0x0c) is supported. */
+#define FEATURE_4BA_WRITE	(1 << 16) /**< Native 4BA byte program (0x12) is supported. */
 /* 4BA Shorthands */
 #define FEATURE_4BA_NATIVE	(FEATURE_4BA_READ | FEATURE_4BA_FAST_READ | FEATURE_4BA_WRITE)
 #define FEATURE_4BA		(FEATURE_4BA_ENTER | FEATURE_4BA_EXT_ADDR | FEATURE_4BA_NATIVE)
 #define FEATURE_4BA_WREN	(FEATURE_4BA_ENTER_WREN | FEATURE_4BA_EXT_ADDR | FEATURE_4BA_NATIVE)
+#define FEATURE_4BA_EAR7	(FEATURE_4BA_ENTER_EAR7 | FEATURE_4BA_EXT_ADDR | FEATURE_4BA_NATIVE)
 /*
  * Most flash chips are erased to ones and programmed to zeros. However, some
  * other flash chips, such as the ENE KB9012 internal flash, work the opposite way.
diff --git a/flashchips.c b/flashchips.c
index 77aa4f7..3022423 100644
--- a/flashchips.c
+++ b/flashchips.c
@@ -12246,7 +12246,7 @@
    	.total_size	= 32768,
    	.page_size	= 256,
    	/* OTP: 1024B total, 32B reserved; read 0x4B; write 0x42 */
-		.feature_bits	= FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_EXT_ADDR,
+		.feature_bits	= FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_ENTER_EAR7,
    	.tested		= TEST_OK_PREW,
    	.probe		= probe_spi_rdid,
    	.probe_timing	= TIMING_ZERO,
diff --git a/flashrom.c b/flashrom.c
index d87a431..c310b98 100644
--- a/flashrom.c
+++ b/flashrom.c
@@ -2227,7 +2227,7 @@
    flash->in_4ba_mode = false;

/* Enable/disable 4-byte addressing mode if flash chip supports it */
-	if (flash->chip->feature_bits & (FEATURE_4BA_ENTER | FEATURE_4BA_ENTER_WREN)) {
+	if (flash->chip->feature_bits & (FEATURE_4BA_ENTER | FEATURE_4BA_ENTER_WREN | FEATURE_4BA_ENTER_EAR7)) {
    	int ret;
    	if (spi_master_4ba(flash))
    		ret = spi_enter_4ba(flash);
diff --git a/spi25.c b/spi25.c
index db4756d..b3f4a87 100644
--- a/spi25.c
+++ b/spi25.c
@@ -853,6 +853,8 @@
    	ret = spi_send_command(flash, sizeof(cmd), 0, &cmd, NULL);
    else if (flash->chip->feature_bits & FEATURE_4BA_ENTER_WREN)
    	ret = spi_simple_write_cmd(flash, cmd, 0);
+	else if (flash->chip->feature_bits & FEATURE_4BA_ENTER_EAR7)
+		ret = spi_set_extended_address(flash, enter ? 0x80 : 0x00);

if (!ret)
    	flash->in_4ba_mode = enter;