[S] Change in flashrom[main]: flashchips: add GD25B256E and GD25R256E

[Anastasia Klimchuk (Code Review)]

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/83998?usp=email )

Change subject: flashchips: add GD25B256E and GD25R256E
......................................................................

flashchips: add GD25B256E and GD25R256E

removed FEATURE_WRSR_EXT2 from the model after datasheet review.
replace
printlock	= SPI_PRETTYPRINT_STATUS_REGISTER_BP3_SRWD,
.unlock		= SPI_DISABLE_BLOCKPROTECT,

with

.printlock	= SPI_PRETTYPRINT_STATUS_REGISTER_BP4_SRWD,
.unlock		= SPI_DISABLE_BLOCKPROTECT_BP4_SRWD,

GD25B256E: 3V 256Mbit, Quad enabled.
GD25R256E: GD25B256E features + RPMC, so they share the same datasheet on flash side
https://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20230627/DS-00...

Tested both models on ch347 with erase, write, read and protection.

Change-Id: Ie733e0c2e35fa4797f5198f2c8334469b65f402c
Signed-off-by: Victor Lim 
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83998
Tested-by: build bot (Jenkins) 
Reviewed-by: Anastasia Klimchuk 
---
M flashchips.c
M include/flashchips.h
2 files changed, 6 insertions(+), 7 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Anastasia Klimchuk: Looks good to me, approved

diff --git a/flashchips.c b/flashchips.c
index 40a3f2b..0c8517f 100644
--- a/flashchips.c
+++ b/flashchips.c
@@ -7583,14 +7583,13 @@

{
    	.vendor		= "GigaDevice",
-		.name		= "GD25Q256D/GD25Q256E",
+		.name		= "GD25Q256E/GD25B256E/GD25R256E/GD25Q256D",
    	.bustype	= BUS_SPI,
    	.manufacture_id	= GIGADEVICE_ID,
    	.model_id	= GIGADEVICE_GD25Q256D,
    	.total_size	= 32768,
    	.page_size	= 256,
-		.feature_bits	= FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA |
-				  FEATURE_WRSR_EXT2 | FEATURE_WRSR2 | FEATURE_WRSR3,
+		.feature_bits	= FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA | FEATURE_WRSR2 | FEATURE_WRSR3,
    	.tested		= TEST_OK_PREWB,
    	.probe		= PROBE_SPI_RDID,
    	.probe_timing	= TIMING_ZERO,
@@ -7622,8 +7621,8 @@
    			.block_erase = SPI_BLOCK_ERASE_C7,
    		}
    	},
-		.printlock	= SPI_PRETTYPRINT_STATUS_REGISTER_BP3_SRWD,
-		.unlock		= SPI_DISABLE_BLOCKPROTECT,
+		.printlock	= SPI_PRETTYPRINT_STATUS_REGISTER_BP4_SRWD,
+		.unlock		= SPI_DISABLE_BLOCKPROTECT_BP4_SRWD, /* TODO: 2nd status reg (read with 0x35) */
    	.write		= SPI_CHIP_WRITE256,
    	.read		= SPI_CHIP_READ,
    	.voltage	= {2700, 3600},
@@ -7632,7 +7631,7 @@
    		.srp    = {STATUS1, 7, RW},
    		.srl    = {STATUS2, 6, RW},
    		.bp     = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 5, RW}},
-			.tb     = {STATUS1, 6, RW},
+			.tb     = {STATUS1, 6, RW},	/* Called BP4 in datasheet, acts like TB */
    	},
    	.decode_range	= DECODE_RANGE_SPI25,
    },
diff --git a/include/flashchips.h b/include/flashchips.h
index 02de72a..4456587 100644
--- a/include/flashchips.h
+++ b/include/flashchips.h
@@ -395,7 +395,7 @@
 #define GIGADEVICE_GD25Q32	0x4016	/* Same as GD25Q32B */
 #define GIGADEVICE_GD25Q64	0x4017	/* Same as GD25Q64B */
 #define GIGADEVICE_GD25Q128	0x4018	/* Same as GD25Q128B, GD25Q127C, GD25Q128C,and GD25Q128E, GD25B128E, GD25R128E can be distinguished by SFDP */
-#define GIGADEVICE_GD25Q256D	0x4019
+#define GIGADEVICE_GD25Q256D	0x4019	/* Same as GD25B256E, GD25Q256E, GD25R256E	*/
 #define GIGADEVICE_GD25VQ21B	0x4212
 #define GIGADEVICE_GD25VQ41B	0x4213  /* Same as GD25VQ40C, can be distinguished by SFDP */
 #define GIGADEVICE_GD25VQ80C	0x4214