Change in flashrom[staging]: fixup! flashrom: Add Skylake platform support

[Nico Huber (Code Review)]

Nico Huber has uploaded a new change for review. ( https://review.coreboot.org/18935 )

Change subject: fixup! flashrom: Add Skylake platform support
......................................................................

fixup! flashrom: Add Skylake platform support

ichspi: Drop odd, constant erase block size mapping

Change-Id: Iab0a8b71a7680b8dee4f7c6c5dabc05c8436d97e
Signed-off-by: Nico Huber 
---
M ichspi.c
1 file changed, 1 insertion(+), 16 deletions(-)

git pull ssh://review.coreboot.org:29418/flashrom refs/changes/35/18935/1

diff --git a/ichspi.c b/ichspi.c
index 16bb2b5..ac859e0 100644
--- a/ichspi.c
+++ b/ichspi.c
@@ -214,15 +214,6 @@
 #define PCH100_REG_OPMENU_LOWER	0xA8	/* 32 Bits */
 #define PCH100_REG_OPMENU_UPPER	0xAC	/* 32 Bits */

-/* The minimum erase block size in PCH which is 4k
-*	256,
-*	4 * 1024,
-*	8 * 1024,
-*	64 * 1024
-*/
-#define ERASE_BLOCK_SIZE 1
-
-
 /* ICH SPI configuration lock-down. May be set during chipset enabling. */
 static int ichspi_lock = 0;

@@ -1464,14 +1455,8 @@
  */
 static uint32_t pch_hwseq_get_erase_block_size(unsigned int addr)
 {
-	static const uint32_t dec_berase[4] = {
-		256,
-		4 * 1024,
-		8 * 1024,
-		64 * 1024
-	};
    pch_hwseq_set_addr(addr);
-	return dec_berase[ERASE_BLOCK_SIZE];
+	return 4 * 1024;
 }

/* Polls for Cycle Done Status, Flash Cycle Error or timeout in 8 us intervals.