Change in flashrom[staging]: fixup! flashrom: Add Skylake platform support

[Nico Huber (Code Review)]

Nico Huber has uploaded a new change for review. ( https://review.coreboot.org/18959 )

Change subject: fixup! flashrom: Add Skylake platform support
......................................................................

fixup! flashrom: Add Skylake platform support

Update pretty-print functions

Change-Id: Ie1d34b3907ab91cce513b0f6b36e1459f91839f6
Signed-off-by: Nico Huber 
---
M ichspi.c
1 file changed, 23 insertions(+), 8 deletions(-)

git pull ssh://review.coreboot.org:29418/flashrom refs/changes/59/18959/1

diff --git a/ichspi.c b/ichspi.c
index ed14338..746b100 100644
--- a/ichspi.c
+++ b/ichspi.c
@@ -37,14 +37,17 @@

/* Added HSFS Status bits */
 #define HSFS_WRSDIS_OFF		11	/* 11: Flash Configuration Lock-Down */
-#define HSFS_WRSDIS		(0x1 << HSFSC_WRSDIS_OFF)
-#define HSFS_PRR34LCKDN_OFF	12	/* 12: PRR3 PRR4 Lock-Down */
-#define HSFS_PRR34LCKDN		(0x1 << HSFSC_PRR34LCKDN_OFF)
+#define HSFS_WRSDIS		(0x1 << HSFS_WRSDIS_OFF)
+#define HSFS_PRR34_LOCKDN_OFF	12	/* 12: PRR3 PRR4 Lock-Down */
+#define HSFS_PRR34_LOCKDN	(0x1 << HSFS_PRR34_LOCKDN_OFF)
 /* HSFS_BERASE vanished */

/* Changed HSFC Control bits */
 #define PCH100_HSFC_FCYCLE_OFF	1	/* 1-4: FLASH Cycle */
 #define PCH100_HSFC_FCYCLE	(0xf << PCH100_HSFC_FCYCLE_OFF)
+/* New HSFC Control bit */
+#define HSFC_WET_OFF		5	/* 5: Write Enable Type */
+#define HSFC_WET		(0x1 << HSFC_WET_OFF)

#define PCH100_FADDR_FLA	0x07ffffff

@@ -371,7 +374,8 @@
    	 ops->preop[1]);
 }

-#define pprint_reg(reg, bit, val, sep) msg_pdbg("%s=%d" sep, #bit, (val & reg##_##bit)>>reg##_##bit##_OFF)
+#define _pprint_reg(bit, mask, off, val, sep) msg_pdbg("%s=%d" sep, #bit, (val & mask) >> off)
+#define pprint_reg(reg, bit, val, sep) _pprint_reg(bit, reg##_##bit, reg##_##bit##_OFF, val, sep)

static void prettyprint_ich9_reg_hsfs(uint16_t reg_val)
 {
@@ -379,8 +383,14 @@
    pprint_reg(HSFS, FDONE, reg_val, ", ");
    pprint_reg(HSFS, FCERR, reg_val, ", ");
    pprint_reg(HSFS, AEL, reg_val, ", ");
-	pprint_reg(HSFS, BERASE, reg_val, ", ");
+	if (ich_generation != CHIPSET_100_SERIES_SUNRISE_POINT) {
+		pprint_reg(HSFS, BERASE, reg_val, ", ");
+	}
    pprint_reg(HSFS, SCIP, reg_val, ", ");
+	if (ich_generation == CHIPSET_100_SERIES_SUNRISE_POINT) {
+		pprint_reg(HSFS, PRR34_LOCKDN, reg_val, ", ");
+		pprint_reg(HSFS, WRSDIS, reg_val, ", ");
+	}
    pprint_reg(HSFS, FDOPSS, reg_val, ", ");
    pprint_reg(HSFS, FDV, reg_val, ", ");
    pprint_reg(HSFS, FLOCKDN, reg_val, "\n");
@@ -390,7 +400,12 @@
 {
    msg_pdbg("HSFC: ");
    pprint_reg(HSFC, FGO, reg_val, ", ");
-	pprint_reg(HSFC, FCYCLE, reg_val, ", ");
+	if (ich_generation != CHIPSET_100_SERIES_SUNRISE_POINT) {
+		pprint_reg(HSFC, FCYCLE, reg_val, ", ");
+	} else {
+		_pprint_reg(HSFC, PCH100_HSFC_FCYCLE, PCH100_HSFC_FCYCLE_OFF, reg_val, ", ");
+		pprint_reg(HSFC, WET, reg_val, ", ");
+	}
    pprint_reg(HSFC, FDBC, reg_val, ", ");
    pprint_reg(HSFC, SME, reg_val, "\n");
 }
@@ -422,12 +437,12 @@
    pprint_reg(DLOCK, BMWAG_LOCKDN, reg_val, ", ");
    pprint_reg(DLOCK, BMRAG_LOCKDN, reg_val, ", ");
    pprint_reg(DLOCK, SBMWAG_LOCKDN, reg_val, ", ");
-	pprint_reg(DLOCK, SBMRAG_LOCKDN, reg_val, ", ");
+	pprint_reg(DLOCK, SBMRAG_LOCKDN, reg_val, ",\n       ");
    pprint_reg(DLOCK, PR0_LOCKDN, reg_val, ", ");
    pprint_reg(DLOCK, PR1_LOCKDN, reg_val, ", ");
    pprint_reg(DLOCK, PR2_LOCKDN, reg_val, ", ");
    pprint_reg(DLOCK, PR3_LOCKDN, reg_val, ", ");
-	pprint_reg(DLOCK, PR4_LOCKDN, reg_val, ", ");
+	pprint_reg(DLOCK, PR4_LOCKDN, reg_val, ",\n       ");
    pprint_reg(DLOCK, SSEQ_LOCKDN, reg_val, "\n");
 }