[S] Change in flashrom[master]: flashchips: Add write protect bits to W25Q64JW...M

[Evan Benn (Code Review)]

Attention is currently required from: Nikolai Artemiev.

Hello Nikolai Artemiev,

I'd like you to do a code review.
Please visit

https://review.coreboot.org/c/flashrom/+/67719

to review the following change.

Change subject: flashchips: Add write protect bits to W25Q64JW...M
......................................................................

flashchips: Add write protect bits to W25Q64JW...M

https://www.winbond.com/hq/support/documentation/levelOne.jsp?__locale=en&am...

BUG=b:245996788
BRANCH=None
TEST=None

Change-Id: Idf2289b7c90724ececc122d2a05c7cae3af2cf62
Signed-off-by: Evan Benn 
---
M flashchips.c
1 file changed, 28 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/flashrom refs/changes/19/67719/1

diff --git a/flashchips.c b/flashchips.c
index 47a37ee..5fa0018 100644
--- a/flashchips.c
+++ b/flashchips.c
@@ -18393,7 +18393,7 @@
    	.page_size	= 256,
    	/* OTP: 256B total; read 0x48; write 0x42, erase 0x44, read ID 0x4B */
    	/* QPI enable 0x38, disable 0xFF */
-		.feature_bits	= FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI,
+		.feature_bits	= FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI | FEATURE_WRSR2 | FEATURE_WRSR3,
    	.tested		= TEST_OK_PREW,
    	.probe		= probe_spi_rdid,
    	.probe_timing	= TIMING_ZERO,
@@ -18421,6 +18421,17 @@
    	.write		= spi_chip_write_256,
    	.read		= spi_chip_read,
    	.voltage	= {1700, 1950}, /* Fast read (0x0B) and multi I/O supported */
+		.reg_bits	=
+		{
+			.srp    = {STATUS1, 7, RW},
+			.srl    = {STATUS2, 0, RW},
+			.bp     = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}},
+			.tb     = {STATUS1, 5, RW},
+			.sec    = {STATUS1, 6, RW},
+			.cmp    = {STATUS2, 6, RW},
+			.wps	= {STATUS3, 2, RW},
+		},
+		.decode_range	= decode_range_spi25,
    },

{