Attention is currently required from: Patrick Georgi, Rizwan Qureshi, Stefan Reinauer, Sridhar Siricilla, Angel Pons, Alex Levin, YH Lin, Martin Roth, Subrata Banik, Caveh Jalali, Tim Wawrzynczak, Nick Vaccaro, Boris Mittelberg.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/61854 )
Change subject: ichspi.c: Check SPI Cycle In-Progress prior start HW Seq
......................................................................
Patch Set 9:
(3 comments)
Commit Message:
https://review.coreboot.org/c/flashrom/+/61854/comment/5e6a2858_62b327e0
PS7, Line 17: Without this synchronisation being implemented, flashrom is running
: into below error:
:
: Erasing and writing flash chip... Timeout error between offset
: 0x0061c000 and 0x0061c03f (= 0x0061c000 + 63)! FAILED!
: Uh oh. Erase/write failed. Checking if anything has changed.
Ack
What I'm still missing is how it relates to the change. AIUI, it's
only the background story what led to its finding, and doesn't say
anything about the change.
I think it's generally ok to add such information (even though I
don't see any value). But it must be clear how it relates to the
change. Confusing information can be harmful, especially in commit
messages that can't be changed later on.
https://review.coreboot.org/c/flashrom/+/61854/comment/1456ac09_f7c86664
PS7, Line 24: BUG=b:215255210
Ack
I don't see any answer. Please never again mark my comments as resolved.
Please make sure all information on that issue tracker is sane, doesn't
lead to further wrong assumptions about this change and can't be changed
anymore, e.g. close the ticket. Or, just don't reference it.
https://review.coreboot.org/c/flashrom/+/61854/comment/250702bc_21c0b6a6
PS7, Line 25: TEST=Concurrent flashrom access is not throwing timeout.
Ack
Please also test older platforms, not just the newest (also, platforms
that are not supported yet don't matter). If you need help with testing
you can always ask on the mailing list and IRC.
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