[S] Change in flashrom[main]: ch347_spi: Add spi clock frequency selection

[Nicholas Chin (Code Review)]

Attention is currently required from: ZhiYuanNJ.

Nicholas Chin has posted comments on this change by ZhiYuanNJ. ( https://review.coreboot.org/c/flashrom/+/82776?usp=email )

Change subject: ch347_spi: Add spi clock frequency selection
......................................................................

Patch Set 5:

(2 comments)

File ch347_spi.c:

https://review.coreboot.org/c/flashrom/+/82776/comment/20c47497_5bef2c78?usp... :
PS5, Line 290: int index = 0;
I just noticed this when testing your patch. If the spispeed isn't set, `divisor` defaults to 1 (30 MHz), but the message in line 370 says 60M because `index` defaults to 0:
```
flashrom 1.4.0-devel (git:v1.2-1460-g59c77b71) on Linux 6.9.4-arch1-1 (x86_64)
flashrom is free software, get the source code at https://flashrom.org

Invalid SPI speed, using 30MHz clock spi.
CH347 SPI clock set to 60M.
```
You could change index to default to 1, but then there would be two variables that need the proper default set. Perhaps rework it so that it only uses `index` (dropping `divisor`) and then determines the value to pass to `ch347_spi_init()` based on that?

https://review.coreboot.org/c/flashrom/+/82776/comment/9e1fd19d_74b923ea?usp... :
PS5, Line 370: 		msg_pinfo("CH347 SPI clock set to %s.\n", spispeeds[index].name);
If the spispeed parameter is invalid, `index` is 8 here, so this prints out `CH347 SPI clock set to (null)`, though `divisor` will still be the default 1 so flashrom will internally proceed with 30 MHz.