[M] Change in flashrom[main]: flashchips: add support for chip model Winbond W25Q32JV_M

[Anastasia Klimchuk (Code Review)]

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/83586?usp=email )

Change subject: flashchips: add support for chip model Winbond W25Q32JV_M
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flashchips: add support for chip model Winbond W25Q32JV_M

This is a 4 MiB model with QE=0 factory setting.

Tested with ch341a programmer: probe, read, write, erase

Link to datasheet:
https://www.winbond.com/resource-files/W25Q32JV%20RevI%2005042021%20Plus.pdf

Change-Id: I374c466848eabf5647dc88e016ac32b99ec37a06
Signed-off-by: Michael Heimpold 
Reviewed-on: https://review.coreboot.org/c/flashrom/+/83586
Tested-by: build bot (Jenkins) 
Reviewed-by: Anastasia Klimchuk 
---
M flashchips.c
M include/flashchips.h
2 files changed, 53 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Anastasia Klimchuk: Looks good to me, approved

diff --git a/flashchips.c b/flashchips.c
index 46b87e3..01cf641 100644
--- a/flashchips.c
+++ b/flashchips.c
@@ -19992,6 +19992,58 @@

{
    	.vendor		= "Winbond",
+		.name		= "W25Q32JV_M",
+		.bustype	= BUS_SPI,
+		.manufacture_id	= WINBOND_NEX_ID,
+		.model_id	= WINBOND_NEX_W25Q32JV_M,
+		.total_size	= 4096,
+		.page_size	= 256,
+		/* supports SFDP */
+		/* OTP: 3x 256B total; read 0x48; write 0x42, erase 0x44, read ID 0x4B */
+		.feature_bits	= FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI |
+				  FEATURE_WRSR2 | FEATURE_WRSR3,
+		.tested		= TEST_OK_PREW,
+		.probe		= PROBE_SPI_RDID,
+		.probe_timing	= TIMING_ZERO,
+		.block_erasers	=
+		{
+			{
+				.eraseblocks = { {4 * 1024, 1024} },
+				.block_erase = SPI_BLOCK_ERASE_20,
+			}, {
+				.eraseblocks = { {32 * 1024, 128} },
+				.block_erase = SPI_BLOCK_ERASE_52,
+			}, {
+				.eraseblocks = { {64 * 1024, 64} },
+				.block_erase = SPI_BLOCK_ERASE_D8,
+			}, {
+				.eraseblocks = { {4 * 1024 * 1024, 1} },
+				.block_erase = SPI_BLOCK_ERASE_60,
+			}, {
+				.eraseblocks = { {4 * 1024 * 1024, 1} },
+				.block_erase = SPI_BLOCK_ERASE_C7,
+			}
+		},
+		.printlock	= SPI_PRETTYPRINT_STATUS_REGISTER_SRWD_SEC_TB_BP2_WELWIP,
+		.unlock		= SPI_DISABLE_BLOCKPROTECT,
+		.write		= SPI_CHIP_WRITE256,
+		.read		= SPI_CHIP_READ,
+		.voltage	= {2700, 3600},
+		.reg_bits	=
+		{
+			.srp    = {STATUS1, 7, RW},
+			.sec    = {STATUS1, 6, RW},
+			.tb     = {STATUS1, 5, RW},
+			.bp     = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}},
+			.cmp    = {STATUS2, 6, RW},
+			.srl    = {STATUS2, 0, RW},
+			.wps    = {STATUS3, 2, RW},
+		},
+		.decode_range	= DECODE_RANGE_SPI25,
+	},
+
+	{
+		.vendor		= "Winbond",
    	.name		= "W25Q32JV",
    	.bustype	= BUS_SPI,
    	.manufacture_id	= WINBOND_NEX_ID,
diff --git a/include/flashchips.h b/include/flashchips.h
index 22509c4..c4b13d9 100644
--- a/include/flashchips.h
+++ b/include/flashchips.h
@@ -1017,6 +1017,7 @@
 #define WINBOND_NEX_W25Q128_W	0x6018	/* W25Q128FW; W25Q128FV in QPI mode */
 #define WINBOND_NEX_W25Q256_W	0x6019	/* W25Q256JW */
 #define WINBOND_NEX_W25Q16JV_M	0x7015	/* W25Q16JV_M (QE=0) */
+#define WINBOND_NEX_W25Q32JV_M	0x7016	/* W25Q32JV_M (QE=0) */
 #define WINBOND_NEX_W25Q64JV	0x7017	/* W25Q64JV */
 #define WINBOND_NEX_W25Q128_V_M	0x7018	/* W25Q128JVSM */
 #define WINBOND_NEX_W25Q256JV_M	0x7019	/* W25Q256JV_M (QE=0) */