Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/22396
to look at the new patch set (#2).
Change subject: spi: Move ICH BBAR quirk out of the way ......................................................................
spi: Move ICH BBAR quirk out of the way
Get rid of the layering violations around ICH's BBAR. Move all the weird address handling into (surprise, surprise) `ichspi.c`. Might fix writes for the `BBAR != 0` case by accident.
Background: Some ICHs have a BBAR (BIOS Base Address Configuration Register) that, if set, limits the valid address range to [BBAR, 2^24). Current code lifted addresses for REMS, RES and READ operations by BBAR, now we do it for all addresses in ichspi. Special care has to be taken if the BBAR is not aligned by the flash chip's size. In this case, the lower part of the chip (from BBAR aligned down, up to BBAR) is inacces- sible (this seems to be the original intend behind BBAR) and has to be left out in the address offset calculation.
Change-Id: Icbac513c5339e8aff624870252133284ef85ab73 Signed-off-by: Nico Huber nico.h@gmx.de --- M flash.h M ichspi.c M programmer.h M spi.c M spi25.c 5 files changed, 28 insertions(+), 83 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/96/22396/2