Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/70549 )
(
7 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: flashchips.c: Add reg_bits for W25Q256JW_DTR ......................................................................
flashchips.c: Add reg_bits for W25Q256JW_DTR
Add reg_bits for W25Q256JW_DTR as per the datasheet.
BUG=b:263410331 TEST=Verified on google/rex.
w/o this patch: Failed to get WP status: WP operations are not implemented for this chip
w/ this patch: flashrom -p internal --wp-range 0x0,0x2000000 flashrom -p internal --wp-enable flashrom -p internal --wp-status flashrom -p internal -E <---- failed to erase the flash as WP (which is expected)
Signed-off-by: Kapil Porwal kapilporwal@google.com Change-Id: I8ac23f706d4293a7d7d11ad6b2f62526fb075367 Reviewed-on: https://review.coreboot.org/c/flashrom/+/70549 Reviewed-by: Subrata Banik subratabanik@google.com Reviewed-by: Edward O'Callaghan quasisec@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M flashchips.c 1 file changed, 42 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Edward O'Callaghan: Looks good to me, approved Subrata Banik: Looks good to me, approved
diff --git a/flashchips.c b/flashchips.c index 625fe62..c24e264 100644 --- a/flashchips.c +++ b/flashchips.c @@ -18108,8 +18108,9 @@ .page_size = 256, /* supports SFDP */ /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA, - .tested = TEST_OK_PREW, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA | FEATURE_WRSR2 + | FEATURE_WRSR3, + .tested = TEST_OK_PREWB, .probe = PROBE_SPI_RDID, .probe_timing = TIMING_ZERO, .block_erasers = @@ -18142,6 +18143,16 @@ .write = SPI_CHIP_WRITE256, .read = SPI_CHIP_READ, .voltage = {1700, 1950}, + .reg_bits = + { + .srp = {STATUS1, 7, RW}, + .srl = {STATUS2, 0, RW}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 5, RW}}, + .tb = {STATUS1, 6, RW}, + .cmp = {STATUS2, 6, RW}, + .wps = {STATUS3, 2, RW}, + }, + .decode_range = DECODE_RANGE_SPI25, },
{