[L] Change in flashrom[master]: Add initial CH347T SPI programmer

[qianfan (Code Review)]

Attention is currently required from: Angel Pons, qianfan.

Hello build bot (Jenkins), Thomas Heijligen, Angel Pons, Nicholas Chin,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/flashrom/+/70529

to look at the new patch set (#8).

Change subject: Add initial CH347T SPI programmer
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Add initial CH347T SPI programmer

Add support for the WCH CH347, a high-speed USB to bus converter
supporting multiple protocols interfaces including SPI. Currently only
mode 1 (vendor defined communication interface) is supported, mode 2
(USB HID communication interface) support will be added later. The code
is currently hard coded to use a CS0 and a SPI clock of 7.5 MHz, though
there are 2 CS lines and 6 other GPIO lines available, as well as a
configurable clock divisor. Support for these will be exposed through
programmer parameters in later commits.

This currently uses the synchronous libusb API. Performance seems to be
alright so far, if it becomes an issue I may switch to the asynchronous
API.

Change-Id: I6da5e308af76693e60308c8165349128e517e09a
Signed-off-by: qianfan Zhao 
Signed-off-by: Nicholas Chin 
Tested-by: Nicholas Chin with MX25L1606E
Tested-by: qianfan Zhao with W25Q16.V
---
M Makefile
A ch347t_spi.c
M include/programmer.h
M programmer_table.c
4 files changed, 547 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/flashrom refs/changes/29/70529/8