[XS] Change in flashrom[main]: chipset_enable.c: Add TGL chipset detection based on SPI PCI ID

[Anastasia Klimchuk (Code Review)]

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/84987?usp=email )

Change subject: chipset_enable.c: Add TGL chipset detection based on SPI PCI ID
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chipset_enable.c: Add TGL chipset detection based on SPI PCI ID

Add detection of Tiger Point chipsets based on SPI controller PCI ID.
Current detection is based on ESPI PCI ID only which limits the
flashrom operability to 2 out of many chipset variants.

TEST=Read flash on a platform with Intel Corporation Tiger Lake-LP
SPI Controller [8086:a0a4] and ISA bridge [0601]: Intel Corporation
Device [8086:a088] ESPI device.

Change-Id: Ie6859d81157760ca03fe34ba5ac311eba5a7c46b
Signed-off-by: Michał Żygowski 
Reviewed-on: https://review.coreboot.org/c/flashrom/+/84987
Tested-by: build bot (Jenkins) 
Reviewed-by: Anastasia Klimchuk 
---
M chipset_enable.c
1 file changed, 2 insertions(+), 0 deletions(-)

Approvals:
  Anastasia Klimchuk: Looks good to me, approved
  build bot (Jenkins): Verified

diff --git a/chipset_enable.c b/chipset_enable.c
index 2adc425..ed53702 100644
--- a/chipset_enable.c
+++ b/chipset_enable.c
@@ -2106,6 +2106,8 @@
    {0x8086, 0x9d84, B_S,    DEP, "Intel", "Cannon Lake U Premium",		enable_flash_pch300},
    {0x8086, 0x0284, B_S,    DEP, "Intel", "Comet Lake U Premium",		enable_flash_pch400},
    {0x8086, 0x0285, B_S,    DEP, "Intel", "Comet Lake U Base",		enable_flash_pch400},
+	{0x8086, 0xa0a4, B_S,    DEP, "Intel", "Tiger Lake LP",			enable_flash_pch500},
+	{0x8086, 0x43a4, B_S,    DEP, "Intel", "Tiger Lake H",			enable_flash_pch500},
    {0x8086, 0xa082, B_S,    DEP, "Intel", "Tiger Lake U Premium",		enable_flash_pch500},
    {0x8086, 0xa088, B_S,    DEP, "Intel", "Tiger Lake UP3",		enable_flash_pch500},
    {0x8086, 0xa141, B_S,    NT,  "Intel", "Sunrise Point Desktop Sample",	enable_flash_pch100},