Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/70388 )
(
2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: chipset_enable.c: add PCI ID for TGL-UP3 ......................................................................
chipset_enable.c: add PCI ID for TGL-UP3
Add PCI ID for the Tiger Lake UP3 (Industrial SKU) SoC.
Change-Id: Ie93af14eb5857bfe51964f6565e475b6249dd407 Signed-off-by: Jan Samek jan.samek@siemens.com Reviewed-on: https://review.coreboot.org/c/flashrom/+/70388 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com Reviewed-by: Anastasia Klimchuk aklm@chromium.org --- M chipset_enable.c 1 file changed, 17 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Anastasia Klimchuk: Looks good to me, but someone else must approve
diff --git a/chipset_enable.c b/chipset_enable.c index b9144d1..480113a 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -2080,6 +2080,7 @@ {0x8086, 0x0284, B_S, DEP, "Intel", "Comet Lake U Premium", enable_flash_pch400}, {0x8086, 0x0285, B_S, DEP, "Intel", "Comet Lake U Base", enable_flash_pch400}, {0x8086, 0xa082, B_S, DEP, "Intel", "Tiger Lake U Premium", enable_flash_pch500}, + {0x8086, 0xa088, B_S, DEP, "Intel", "Tiger Lake UP3", enable_flash_pch500}, {0x8086, 0xa141, B_S, NT, "Intel", "Sunrise Point Desktop Sample", enable_flash_pch100}, {0x8086, 0xa142, B_S, NT, "Intel", "Sunrise Point Unknown Sample", enable_flash_pch100}, {0x8086, 0xa143, B_S, DEP, "Intel", "H110", enable_flash_pch100},