Change in flashrom[master]: chipset_enable: Add Kaby Lake U Prem. to known and tested systems

[Wim Vervoorn (Code Review)]

Wim Vervoorn has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/38481 )

Change subject: chipset_enable: Add Kaby Lake U Prem. to known and tested systems
......................................................................

chipset_enable: Add Kaby Lake U Prem. to known and tested systems

Intel Kaby Lake U (with the 9d4e device id) is available but marked not
tested.

This device was tested on the Facebook Monolith system with the Intel i3
7100U SoC.

Signed-off-by: Wim Vervoorn 
Change-Id: Ie35cc896e29baffa63fe9e37c14770001b54e7ec
---
M chipset_enable.c
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/flashrom refs/changes/81/38481/1

diff --git a/chipset_enable.c b/chipset_enable.c
index e826d90..3b44d93 100644
--- a/chipset_enable.c
+++ b/chipset_enable.c
@@ -1989,7 +1989,7 @@
    {0x8086, 0x9d46, B_S,    NT,  "Intel", "Skylake Y Premium",		enable_flash_pch100},
    {0x8086, 0x9d48, B_S,    NT,  "Intel", "Skylake U Premium",		enable_flash_pch100},
    {0x8086, 0x9d4b, B_S,    NT,  "Intel", "Kaby Lake Y w/ iHDCP2.2 Prem.",	enable_flash_pch100},
-	{0x8086, 0x9d4e, B_S,    NT,  "Intel", "Kaby Lake U w/ iHDCP2.2 Prem.",	enable_flash_pch100},
+	{0x8086, 0x9d4e, B_S,    DEP, "Intel", "Kaby Lake U w/ iHDCP2.2 Prem.",	enable_flash_pch100},
    {0x8086, 0x9d50, B_S,    NT,  "Intel", "Kaby Lake U w/ iHDCP2.2 Base",	enable_flash_pch100},
    {0x8086, 0x9d51, B_S,    NT,  "Intel", "Kabe Lake w/ iHDCP2.2 Sample",	enable_flash_pch100},
    {0x8086, 0x9d53, B_S,    NT,  "Intel", "Kaby Lake U Base",		enable_flash_pch100},

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/38481 )

Change subject: chipset_enable: Add Kaby Lake U Prem. to known and tested systems
......................................................................

Patch Set 1: Code-Review+1

(1 comment)

https://review.coreboot.org/c/flashrom/+/38481/1//COMMIT_MSG 
Commit Message:

PS1: 
I would suggest using CB:37803 as a reference for the commit message.

[Wim Vervoorn (Code Review)]

Hello Angel Pons, Frans Hendriks, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/flashrom/+/38481

to look at the new patch set (#2).

Change subject: chipset_enable: Add Kaby Lake U Prem. to known and tested systems
......................................................................

chipset_enable: Add Kaby Lake U Prem. to known and tested systems

Intel Kaby Lake U (with the 9d4e device id) support is available but marked not
tested.

Tested reading, writing and erasing both internal flash chips on the Facebook Monolith
system with the Intel i3 7100U SoC. However, since all ME-enabled chipsets are marked
as DEP instead of OK, this one shall follow suit as well.

Signed-off-by: Wim Vervoorn 
Change-Id: Ie35cc896e29baffa63fe9e37c14770001b54e7ec
---
M chipset_enable.c
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/flashrom refs/changes/81/38481/2

[Wim Vervoorn (Code Review)]

Wim Vervoorn has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/38481 )

Change subject: chipset_enable: Add Kaby Lake U Prem. to known and tested systems
......................................................................

Patch Set 2:

(1 comment)

https://review.coreboot.org/c/flashrom/+/38481/1//COMMIT_MSG 
Commit Message:

PS1:
> I would suggest using CB:37803 as a reference for the commit message.

Done

[Wim Vervoorn (Code Review)]

Wim Vervoorn has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/38481 )

Change subject: chipset_enable: Add Kaby Lake U Prem. to known and tested systems
......................................................................

Patch Set 2:

(1 comment)

https://review.coreboot.org/c/flashrom/+/38481/1//COMMIT_MSG 
Commit Message:

PS1:
> Done

Done

[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/38481 )

Change subject: chipset_enable: Add Kaby Lake U Prem. to known and tested systems
......................................................................

Patch Set 2:

(1 comment)

https://review.coreboot.org/c/flashrom/+/38481/2//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/flashrom/+/38481/2//COMMIT_MSG@14 
PS2, Line 14: as DEP instead of OK, this one shall follow suit as well.
Commit messages still have a line length limit of 75 characters. Please reflow.

[Wim Vervoorn (Code Review)]

Hello Angel Pons, Frans Hendriks, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/flashrom/+/38481

to look at the new patch set (#3).

Change subject: chipset_enable: Add Kaby Lake U Prem. to known and tested systems
......................................................................

chipset_enable: Add Kaby Lake U Prem. to known and tested systems

Intel Kaby Lake U (with the 9d4e device id) support is available but
marked not tested.

Tested reading, writing and erasing both internal flash chips on the
Facebook Monolith system with the Intel i3 7100U SoC. However, since all
ME-enabled chipsets are marked as DEP instead of OK, this one shall follow
suit as well.

Signed-off-by: Wim Vervoorn 
Change-Id: Ie35cc896e29baffa63fe9e37c14770001b54e7ec
---
M chipset_enable.c
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/flashrom refs/changes/81/38481/3

[Wim Vervoorn (Code Review)]

Wim Vervoorn has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/38481 )

Change subject: chipset_enable: Add Kaby Lake U Prem. to known and tested systems
......................................................................

Patch Set 3:

(1 comment)

https://review.coreboot.org/c/flashrom/+/38481/2//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/flashrom/+/38481/2//COMMIT_MSG@14 
PS2, Line 14: as DEP instead of OK, this one shall follow suit as well.
> Commit messages still have a line length limit of 75 characters. Please reflow.

Done

[Nico Huber (Code Review)]

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/38481 )

Change subject: chipset_enable: Add Kaby Lake U Prem. to known and tested systems
......................................................................

Patch Set 3: Verified+1 Code-Review+2

(1 comment)

https://review.coreboot.org/c/flashrom/+/38481/2//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/flashrom/+/38481/2//COMMIT_MSG@14 
PS2, Line 14: as DEP instead of OK, this one shall follow suit as well.
> Done

Actually, 72 characters.

[Nico Huber (Code Review)]

Nico Huber has submitted this change. ( https://review.coreboot.org/c/flashrom/+/38481 )

Change subject: chipset_enable: Add Kaby Lake U Prem. to known and tested systems
......................................................................

chipset_enable: Add Kaby Lake U Prem. to known and tested systems

Intel Kaby Lake U (with the 9d4e device id) support is available but
marked not tested.

Tested reading, writing and erasing both internal flash chips on the
Facebook Monolith system with the Intel i3 7100U SoC. However, since all
ME-enabled chipsets are marked as DEP instead of OK, this one shall follow
suit as well.

Signed-off-by: Wim Vervoorn 
Change-Id: Ie35cc896e29baffa63fe9e37c14770001b54e7ec
Reviewed-on: https://review.coreboot.org/c/flashrom/+/38481
Tested-by: Nico Huber 
Reviewed-by: Nico Huber 
Reviewed-by: Angel Pons 
---
M chipset_enable.c
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Nico Huber: Verified; Looks good to me, approved
  Angel Pons: Looks good to me, but someone else must approve

diff --git a/chipset_enable.c b/chipset_enable.c
index e826d90..3b44d93 100644
--- a/chipset_enable.c
+++ b/chipset_enable.c
@@ -1989,7 +1989,7 @@
    {0x8086, 0x9d46, B_S,    NT,  "Intel", "Skylake Y Premium",		enable_flash_pch100},
    {0x8086, 0x9d48, B_S,    NT,  "Intel", "Skylake U Premium",		enable_flash_pch100},
    {0x8086, 0x9d4b, B_S,    NT,  "Intel", "Kaby Lake Y w/ iHDCP2.2 Prem.",	enable_flash_pch100},
-	{0x8086, 0x9d4e, B_S,    NT,  "Intel", "Kaby Lake U w/ iHDCP2.2 Prem.",	enable_flash_pch100},
+	{0x8086, 0x9d4e, B_S,    DEP, "Intel", "Kaby Lake U w/ iHDCP2.2 Prem.",	enable_flash_pch100},
    {0x8086, 0x9d50, B_S,    NT,  "Intel", "Kaby Lake U w/ iHDCP2.2 Base",	enable_flash_pch100},
    {0x8086, 0x9d51, B_S,    NT,  "Intel", "Kabe Lake w/ iHDCP2.2 Sample",	enable_flash_pch100},
    {0x8086, 0x9d53, B_S,    NT,  "Intel", "Kaby Lake U Base",		enable_flash_pch100},